1. A system comprising:
a processor;
a dynamic pinning remote direct memory access helper on the processor core; and
a network interface controller comprising:
a network interface to connect the network interface controller to a second network interface controller on a remote computing node;
a system bus interface to connect the network interface controller to the processor via a system bus;
buffers usable as cacheable memory regions for the processor; and
a direct memory access engine communicatively coupled to the dynamic pinning remote direct memory access helper via the system bus interface and to receive a request for data,
the dynamic pinning remote direct memory access helper to:
decompose the data to be transferred through a remote direct memory access into at least first and second remote sections, each of the first and second sections being less than an entire memory page;
pin the first remote section until a first portion of the data from the first remote section is transferred to the remote computing node;
after the first portion of the data is transferred, release the first remote section;
after releasing the first remote section, pin the second remote section until a second portion of the data from the second remote section is transferred to the remote computing node; and
after the second portion of the data is transferred, release the second remote section, wherein the first section is pinned at a first time and for a first duration sufficient to transfer the first section, and the second section is pinned at a second time for a second duration sufficient to transfer the second section.
2. The system of claim 1, wherein the system is implemented on a single chip and the processor comprises a processor core.
3. The system of claim 1, wherein the dynamic pinning remote direct memory access helper is to create local sections to receive second data decomposed into third and fourth remote sections on the remote computing node, and to sequentially pin and release each of third and fourth local sections separately as the second data is sequentially transferred into the third and fourth local sections; and
the direct memory access engine is to perform a second remote direct memory access for each local section.
4. A system comprising:
a dynamic pinning remote direct memory access helper in a kernel on a processor,
for a request for data, the dynamic pinning remote direct memory access helper to:
create at least first and second local sections to receive the data decomposed into at least first and second remote sections on a remote computing node,
pin the first local section until a first portion of the data from the first remote section is received,
after the first portion of the data is received, release the first local section,
after releasing the first local section, pin the second local section until a second portion of the data from the second remote section is received, and
after the second portion of the data is received, release the second local section; and
a direct memory access engine to perform a remote direct memory access for each local section via the network interface until all of the data is received.
5. The system of claim 4, further comprising:
a swapper in the kernel, wherein when a head of a remaining local section is not resident in memory, the swapper is to swap the head into memory.
6. The system of claim 4, further comprising a virtual network interface controller layer to provide a datagram service to receive frames of data for each local section.
7. The system of claim 4, further comprising a registered virtual buffer mapped to physical memory, each local section being in the virtual buffer.
8. The chip of claim 7, further comprising:
system memory, at least one of the sections being a remote section of a send side node, the network interface controller to perform the remote direct memory access by retrieving the remote section from addresses in the system memory and transferring the remote section from the network interface controller to a network interface controller in a receive side node via a network.
9. The chip of claim 7, further comprising:
system memory, at least one of the sections being a local section of a receive side node, and the region of memory is received at the network interface controller and stored in the local section.
10. The chip of claim 7, further comprising:
a kernel on the processor core, the kernel including the dynamic pinning remote direct memory access helper.
11. The system of claim 4, wherein:
the dynamic pinning remote direct memory access helper is to decompose second data to be transferred through a second remote direct memory access into third and fourth remote sections and to dynamically pin and release the third and fourth remote sections separately as the second data is transferred into the third and fourth remote sections; and
the direct memory access engine is to perform the second remote direct memory access for each remote section via the network interface until the second data is transferred.
12. The system of claim 4, wherein the system is implemented on a single chip and the processor comprises a processor core.
13. A chip comprising:
a processor core;
a dynamic pinning remote direct memory access helper on the processor core; and
a network interface controller communicatively coupled to the dynamic pinning remote direct memory access helper, the network interface controller to perform a remote direct memory access of a region of memory for a request for data, the dynamic pinning remote direct memory access helper to:
decompose the region of memory into at least first and second sections,
pin the first section until a first portion of the region of memory is accessed;
after the first portion of the region of memory is accessed, release the first section;
after releasing the first section, pin the second section until a second portin of the region of memory is accessed; and
after the second portion of the region of memory is accessed, release the second section.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for monitoring relative movement of a surface area, comprising:
a host computer;
a grid of sensors at known distances from each other, spaced within the surface area;
wherein the host computer is operable to wirelessly and individually instruct each sensor to operate in an interrogator mode or a responder mode;
wherein each sensor has radar circuitry for sending and receiving a continuous wave signal, such that it may send the signal to, and receive the signal back from, a neighboring sensor, when the former sensor is in interrogate mode;
wherein each sensor has delay circuitry for delaying and returning a signal received from a neighboring sensor, when the former sensor is in responder mode;
wherein each sensor has control circuitry for determining whether the sensor is in interrogator or responder mode and for calculating phase difference measurements of a returned signal.
2. The system of claim 1, wherein each sensor has an omni-directional antenna.
3. The system of claim 1, wherein the known distances are known to within one-half of the wavelength of the continuous wave.
4. The system of claim 1, wherein the control unit of each sensor is further operable to transmit distance measurement data to the host computer.
5. The system of claim 1, wherein each sensor further has initialization circuitry for using a pulse burst radar process to determine the inter-sensor distances with an accuracy of less than the carrier wavelength.
6. The system of claim 1, wherein the host computer and sensors wirelessly communicate using a wireless LAN communications standard.
7. The system of claim 1, wherein the inter-sensor spacing is sufficiently close such that they are operational at 1 mW of power of less.
8. The system of claim 1, wherein the host computer and sensors are operational at a single carrier frequency.
9. A method of monitoring relative movement of a surface area, comprising:
placing a grid of sensors at known distances from each other, spaced within the defined area;
using a host computer to wirelessly and individually instruct each sensor to operate in an interrogator mode or a responder mode;
wherein each sensor has radar circuitry for sending and receiving a continuous wave signal, such that it may send the signal to, and receive the signal back from a neighboring sensor, when the former sensor is in interrogator mode;
wherein each sensor has delay circuitry for delaying and returning a signal received from a neighboring sensor, when the former sensor is in responder mode;
wherein each sensor has control circuitry for determining whether the sensor is in interrogator or responder mode and for calculating phase difference measurements of the returned signal.
10. The method of claim 9, wherein each sensor has an omni-directional antenna.
11. The method of claim 9, wherein the known distances are known to within one-half of the wavelength of the continuous wave.
12. The method of claim 9, wherein the control unit of each sensor is further operable to transmit distance measurement data to the host computer.
13. The method of claim 9, wherein each sensor further has initialization circuitry for using a pulse burst radar process to determine the inter-sensor distances with an accuracy of less than the carrier wavelength.
14. The method of claim 9, wherein the host computer and sensors wirelessly communicate using a wireless LAN communications standard.
15. The method of claim 9, wherein the inter-sensor spacing is sufficiently close such that they are operational at 1 mW of power of less.
16. The method of claim 9, wherein the host computer and sensors are operational at a single carrier frequency.