1. A circuit comprising:
an auto-precharge control circuit for varying a write recovery time of a semiconductor device based on an auto-precharge pulse signal and in response to latency information and clock frequency information included in at least one control signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation.
2. The circuit of claim 1 said auto-precharge control circuit receives a clock signal, a write signal, an auto-precharge command, an active signal, and said at least one control signal and produces the auto-precharge pulse signal.
3. The circuit of claim 2, wherein said auto-precharge control circuit includes
a control circuit for receiving the write signal and the control signal and selecting the starting point for the auto-precharge operation in accordance with the at least one control signal.
4. The circuit of claim 2, further including,
an auto-precharge enabling circuit for receiving the auto-precharge pulse signal and disabling the active signal, thereby starting said auto-precharge operation.
5. The circuit of claim 2, wherein the at least one control signal is generated from an externally supplied mode register setting (MRS) command.
6. The circuit of claim 5, wherein the MRS command further includes at least one of mode information, burst type information, and burst length information.
7. A circuit comprising:
an auto-precharge control circuit for varying a write recovery time of a semiconductor device based on an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation, the write recovery time being varied in response to latency information included in at least one control signal.
8. The circuit of claim 7, wherein the write recovery time is proportional to the latency information.
9. The circuit of claim 7, wherein said auto-precharge control circuit receives a clock signal, a write signal, an auto-precharge command, an active signal, and said at least one control signal and produces the auto-precharge pulse signal.
10. The circuit of claim 7, wherein said auto-pre charge control circuit includes,
a control circuit for receiving the write signal and the control signal and selecting the starting point for the auto-precharge operation in accordance with the at least one control signal.
11. The circuit of claim 7, wherein said auto-precharge control circuit includes,
an auto-precharge enabling circuit for receiving the auto-precharge pulse signal and disabling the active signal, thereby starting said auto-precharge operation.
12. The circuit of claim 7, wherein the latency information is CAS latency information.
13. The circuit of claim 7, wherein the at least one control signal is generated by an externally supplied mode register setting (MRS) command.
14. The circuit of claim 13, wherein the MRS command further includes at least one of mode information, burst type information, and burst length information.
15. A circuit comprising:
an auto-precharge control circuit for varying the number of clock cycles for a write recovery time of a semiconductor device based on an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation, the write recovery time being varied in response to latency information included in at least one control signal.
16. An auto-precharge control circuit, comprising:
a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal;
an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and
an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.
17. The auto-precharge control circuit of claim 16, said auto-precharge mode enabling circuit further comprising:
a feedback signal generator for receiving the auto-precharge pulse signal and outputting a feedback signal to disable the active signal, thereby starting said auto-precharge operation,
an auto-precharge operation selector for forwarding the auto-precharge command in response to the clock signal, the write signal, and the active signal,
said auto-precharge enabling circuit for receiving the active signal and the auto-precharge command and forwarding the enable signal to said auto-precharge pulse signal driver.
18. The auto-precharge control circuit of claim 16, said control circuit including,
a first path including a first switch, receiving the write signal and triggered by the clock signal, and a first latch circuit for generating a first path signal, and
a second path including the first switch, and the first latch circuit of said first path and further including a second switch triggered by the clock signal, a second latch circuit outputting a latch signal and a logic circuit receiving the latch signal and the at least one control signal and generating a second path signal.
19. The auto-precharge control circuit of claim 16, said control circuit including,
at least a first path including a switch triggered by the clock signal, and a latch circuit for generating a first path signal and
a second path including the switch, and the latch circuit of said first path and further including a logic circuit receiving a signal from the latch circuit and the at least one control signal and a delay circuit for delaying the first path signal and generating a second path signal.
20. The auto-precharge control circuit of claim 19, said delay circuit further including, an inverter, a resistor, and a capacitor for outputting the second path signal.
21. The auto-precharge control circuit of claim 16, said control circuit including,
a cascade of circuits in series, each circuit receiving the write signal, the clock signal and at least one control signal, and delaying the write signal by a different amount, depending on the at least one control signal and outputting at least one path signal.
22. The auto-precharge control circuit of claim 21, a first circuit of said cascade of circuits including a NAND gate, an inverter, a switch, a latch circuit, and a switch for generating and outputting a path signal to a subsequent circuit,
subsequent circuits of said cascade of circuits including a NAND gate, a NAND gate, a switch, a latch circuit, and a switch and outputting a path signal to a subsequent circuit, and
a last circuit of said cascade of circuits including a NAND gate, a NAND gate, a switch, and a latch circuit.
23. A method of performing an auto-precharge operation comprising:
varying a write recovery time of a semiconductor device based on an auto-precharge pulse signal and in response to latency information and clock frequency information included in at least one control signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation.
24. The method of claim 23, said method further including,
receiving a clock signal, a write signal, an auto-precharge command, an active signal, and said at least one control signal and producing the auto-precharge pulse signal.
25. The method of claim 23, said method further including,
receiving the write signal and the control signal and selecting the starting point for the auto-precharge operation in accordance with the at least one control signal.
26. The method of claim 23, said method further including,
receiving the auto-precharge pulse signal and disabling the active signal, thereby starting said auto-precharge operation.
27. The method of claim 23, wherein the at least one control signal is generated from an externally supplied mode register setting (MRS) command.
28. The method of claim 27, wherein the MRS command further includes at least one of mode information, burst type information, and burst length information.
29. A method of performing an auto-precharge operation comprising
varying a write recovery time of a semiconductor device based on an auto-precharge pulse signal and in response to latency information included in at least one control signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation.
30. A method of performing an auto-precharge operation comprising:
varying the number of clock cycles for a write recovery time of a semiconductor device based on an auto-precharge pulse signal and in response to latency information included in at least one control signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation.
31. The method of claim 30, wherein the write recovery time is proportional to the latency information.
32. The method of claim 30, said method further including,
receiving a clock signal, a write signal, an auto-precharge command, an active signal, and said at least one control signal, and
producing an auto-precharge pulse signal.
33. The method of claim 30, said method further including,
receiving the write signal and the control signal, and
selecting the starling point for the auto-precharge operation in accordance with the at least one control signal including latency information.
34. The method of claim 30, said method further including,
receiving the auto-precharge pulse signal and disabling the active signal, thereby starting said auto-precharge operation.
35. The method of claim 30, wherein the latency information is CAS latency information.
36. The method of claim 30, wherein the at least one control signal is generated by an externally supplied mode register setting (MRS) command.
37. The method of claim 36, wherein the MRS command further includes at least one of mode information, burst type information, and burst length information.
38. A method of performing an auto-precharge operation, comprising:
an auto-precharge control step for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal;
an auto-precharge pulse signal driving step for receiving the at least one path signal the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and
an auto-precharge mode enabling step for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.
39. The method of claim 38, said auto-precharge mode enabling step further comprising:
a feedback signal generating sub-step for receiving the auto-precharge pulse signal and outputting a feedback signal to disable the active signal, thereby starting said auto-precharge operation,
an auto-precharge operation selecting sub-step for forwarding the auto-precharge command in response to the clock signal, the write signal, and the active signal,
an auto-precharge enabling sub-step for receiving the active signal and the auto-precharge command and forwarding the enable signal to said auto-precharge pulse signal driving step.
40. The method of claim 38, said auto-precharge control step including, generating a first path signal by receiving and processing the write signal, triggered by the clock signal, through a first switch and a first latch circuit, and
generating a second path signal by receiving and processing the write signal, triggered by the clock signal, through the first switch, the first latch circuit, a second switch, a second latch circuit, and a logic circuit.
41. The method of claim 38, said auto-precharge control step including, generating a first path signal by receiving and processing the write signal, triggered by the clock signal, through a switch and a latch circuit, and
generating a second path signal by receiving and processing the write signal, triggered by the clock signal, through the switch, the latch circuit, and a logic circuit receiving a signal from the latch circuit and the at least one control signal and a delay circuit for delaying the first path signal and generating the second path signal.
42. The method of claim 41, the delay circuit including, an inverter, a resistor, and a capacitor for outputting the second path signal.
43. The method of claim 38, said auto-precharge control step including, receiving the write signal, the clock signal and at least one control signal in each of a cascade of circuits in series, and delaying the write signal in each of the cascade of circuits by a different amount, depending on the at least one control signal and outputting at least one path signal.
44. The method of claim 43, a first circuit of the cascade of circuits including a NAND gate, an inverter, a switch, a latch circuit, and a switch or generating and outputting a path signal to a subsequent circuit, subsequent circuits of the cascade of circuits including a NAND gate, a NAND gate, a switch, a latch circuit, and a switch and outputting a path signal to a subsequent circuit, and
a last circuit of the cascade of circuits including a NAND gate, a NAND gate, a switch, and a latch circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A regulated fluid dispensing device especially adapted for dispensing carbonated beverages, said dispensing device comprising:
a main housing having a cavity, and a fluid regulator mounted therein;
a pressure relief mechanism incorporated in said main housing;
a source of compressed gas for supplying a flow of gas through said regulator into a beverage container attached to said dispensing device;
a tap handle operatively connected to said main housing for selectively allowing the beverage to flow through said dispensing device, said tap handle having a cam and a stop arm attached to a base portion of said tap handle;
said main housing further including an outlet sub-housing surrounding said base of said tap handle, said outlet sub-housing having an interior rim and a projection formed on said rim; and
a fluid delivery tube extending through said dispensing device for delivering the beverage, said cam of said tap handle selectively engaging and disengaging said fluid delivery tube to allow beverage to flow therethrough, or to shut off flow of beverage through said fluid delivery tube, and wherein said stop arm of said tap handle frictionally engages said projection when said tap handle is placed in a closed position to shut off the flow of beverage through said delivery tube.
2. A device, as claimed in claim 1, further including:
a sleeve for providing structural support to said fluid delivery tube, said fluid delivery tube extending through said sleeve and said sleeve being located within said main housing.
3. A method of dispensing a beverage from a pressurized beverage container, said method comprising:
providing a dispensing device secured to the beverage container, said device including an integral regulator and an integral pressure release mechanism, said device further including a fluid delivery tube extending through the device and communicating with the beverage container for conveying the beverage for dispensing, a source of pressurized gas communicating with the regulator for maintaining the beverage container at a desired pressure, a tap handle rotatably connected to the dispensing device, said tap handle, including a cam and a stop arm;
positioning the tap handle in a closed position such that the cam makes contact with said fluid delivery tube to prevent the beverage from flowing therethrough, and wherein the stop arm contacts a projection formed in the housing to maintain frictional resistance to maintain said tap handle in the closed position;
rotating the tap handle from the closed position to an open position wherein the cam is rotated away from contact with the fluid delivery tube thereby allowing the beverage to flow through the delivery tube to thereby dispense the beverage through an outlet defined by a distal end of the fluid delivery tube, and wherein the stop arm is disengaged from the projection.