1. A method for transmitting a sounding reference symbol (SRS) comprising:
defining, in conjunction with carrier aggregation, a SRS configuration for a plurality of uplink component carriers (UL CCs) being aggregated for use by one user equipment transmitter,
the SRS configuration comprising:
a specification of a first plurality of offset values, the first plurality of offset values specifying offsets for transmission of SRS on a primary component carrier (PCC); and
a specification of a plurality of secondary offset value indicators, each respective secondary offset value indicator in the plurality of secondary offset value indicators indicating a respective offset value within the first plurality of offset values;
determining whether a SRS and other uplink channels are transmitted in the Physical Uplink Shared Channel (PUSCH) on multiple uplink (UL) component carriers (CCs) in a subframe; and,
specifying, based on determining that the SRS and the other uplink channels are transmitted in the PUSCH on multiple uplink component carriers, a multiplexing rule for simultaneous transmission during the subframe of a SRS transmission and the other uplink channels on the multiple uplink component carriers,
the specifying the multiplexing rule comprising specifying transmission of an SRS on at least one secondary component carrier (SCC) with at least one secondary offset value indicator within the plurality of secondary offset value indicators.
2. The method of claim 1 wherein:
simultaneous transmission of SRS on a first uplink component carrier and other uplink channels in the PUSCH on uplink component carriers different from the first uplink component carrier during a SRS symbol is not allowed.
3. The method of claim 2 wherein:
the SRS transmission is dropped when a SRS transmission collides with a transmission on the different uplink component carrier.
4. The method of claim 2 wherein:
SRS is transmitted with other uplink channels in the same subframe when other uplink channels are transmitted in the PUSCH with SRS in the same uplink component carrier.
5. The method of claim 2 wherein:
other uplink channels to be transmitted on a secondary uplink component carrier are dropped based on transmitting the SRS on a primary uplink component carrier that is different than the secondary uplink component carrier.
6. The method of claim 1 wherein:
simultaneous transmission of SRS during a SRS symbol on at least one uplink component carrier and other uplink channels on different uplink component carriers during the SRS symbol is allowed.
7. The method of claim 6 further comprising:
simultaneously transmitting, without restriction, SRS in the last symbol on a first uplink component carrier and other uplink channels in the last symbol on other uplink component carriers that are different than the first uplink component carrier.
8. The method of claim 1 further comprising:
applying an indication of whether simultaneous transmission of SRS and other uplink channels is allowed.
9. The method of claim 1, wherein the determining further comprises determining whether the SRS and the other uplink channels are transmitted by a single user device on the multiple uplink (UL) component carriers (CCs) in the subframe.
10. The method of claim 1, wherein the plurality of secondary offset value indicators indicate a subset of offset values within the plurality of offset values, the subset of offset values having fewer elements that the plurality of offset values.
11. The method of claim 1,
wherein the defining the SRS configuration comprises defining a table specifying the plurality of secondary offset value indicators, and
wherein the specifying at least one secondary value offset indicator comprises specifying a respective index into the table.
12. The method of claim 1, the specifying the multiplexing rule further comprising specifying transmission of an SRS on the primary component carrier (SCC) by indicating at least one offset value within the first plurality of offset values.
13. An apparatus for transmitting a sounding reference symbol (SRS) comprising:
a processor;
memory coupled to the processor, the memory storing instructions executable by the processor for:
defining, in conjunction with carrier aggregation, a SRS configuration for a plurality of uplink component carriers (UL CCs) being aggregated for use by one user equipment transmitter,
the SRS configuration comprising:
a specification of a first plurality of offset values, the first plurality of offset values specifying offsets for transmission of SRS on a primary component carrier (PCC); and
a specification of a plurality of secondary offset value indicators, each respective secondary offset value indicator in the plurality of secondary offset value indicators indicating a respective offset value within the first plurality of offset values;
determining whether a SRS and other uplink channels are transmitted in the Physical Uplink Shared Channel (PUSCH) on multiple uplink (UL) component carriers (CCs) in a subframe; and,
specifying, based on determining that the SRS and the other uplink channels are transmitted in the PUSCH on multiple uplink component carriers, a multiplexing rule for simultaneous transmission during the subframe of a SRS transmission and the other uplink channels on the multiple uplink component carriers,
the specifying the multiplexing rule comprising specifying transmission of an SRS on at least one secondary component carrier (SCC) with at least one secondary offset value indicator within the plurality of secondary offset value indicators.
14. The apparatus of claim 13 wherein the memory further comprises instructions for:
applying an indication of whether simultaneous transmission of SRS and other uplink channels is allowed.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for performing a sensing operation in a memory device, the method comprising:
connecting a channel of an unselected NAND string in the memory device to a bit line while the bit line is at a driven voltage, wherein the bit line is connected to a selected NAND string, a select gate line is connected to a drain-side select gate transistor at a drain-side of the unselected NAND string and a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy word line is connected to a first dummy memory cell in the unselected NAND string adjacent to the drain-side select gate transistor of the unselected NAND string and to a first dummy memory cell in the selected NAND string adjacent to the drain-side select gate transistor of the selected NAND string, a selected word line is connected to a selected memory cell in the selected NAND string and to a corresponding unselected memory cell in the unselected NAND string, unselected word lines are connected to unselected memory cells in the selected NAND string and to corresponding unselected memory cells in the unselected NAND string, and the connecting comprises requesting a voltage driver of the select gate line to provide a step up of a voltage on the select gate line, requesting a voltage driver of the first dummy word line to provide a first step up of a voltage on the first dummy word line, and requesting a voltage driver of the unselected word lines to provide a first step up of a voltage on the unselected word lines;
after the connecting, disconnecting the channel of the unselected NAND string from the bit line, the disconnecting comprising requesting the voltage driver of the select gate line to provide a step down of the voltage on the select gate line; and
while the channel of the unselected NAND string is disconnected from the bit line:
requesting the voltage driver of the unselected word lines to provide a second step up of the voltage of the unselected word lines,
requesting the voltage driver of the first dummy word line to provide a second step up of the voltage of the first dummy word line,
requesting a voltage driver of the selected word line to provide one or more voltages on the selected word line, and
sensing the selected memory cell while the selected word line is at the one or more voltages.
2. The method of claim 1, wherein:
the second step up of the voltage on the first dummy word line occurs after the second step up of the voltage on the unselected word lines.
3. The method of claim 2, wherein:
a time interval between the second step up of the voltage on the first dummy word line and the second step up of the voltage on the unselected word lines is at least as long as a time interval in which the channel of the unselected NAND string is connected to the bit line during the connecting.
4. The method of claim 3, wherein:
the time interval in which the channel of the unselected NAND string is connected to the bit line during the connecting is a time interval in which a control gate-to-drain voltage of the drain-side select gate transistor of the drain-side of the unselected NAND string exceeds a threshold voltage of the drain-side select gate transistor of the drain-side of the unselected NAND string.
5. The method of claim 1, wherein:
the step up of the voltage on the select gate line occurs concurrently with the first step up of the voltage on the first dummy word line and the first step up of the voltage on the unselected word lines.
6. The method of claim 1, wherein:
the step up of the voltage on the select gate line occurs before the first step up of the voltage on the first dummy word line and the first step up of the voltage on the unselected word lines.
7. The method of claim 1, wherein:
a time interval between the step up of the voltage of the select gate line and the step down of the voltage of the select gate line is insufficient for the voltage of the select gate line to reach a steady state voltage.
8. The method of claim 1, wherein:
a level of the first step up of the voltage on the first dummy word line and a level of the second step up of the voltage on the first dummy word line increase periodically over a lifetime of the memory device.
9. The method of claim 1, further comprising:
measuring an increase in a threshold voltage distribution of a set of dummy memory cells connected to the first dummy word line; and
increasing a level of the first step up of the voltage on the first dummy word line and a level of the second step up of the voltage on the first dummy word line in response to the measuring.
10. The method of claim 1, wherein:
a second dummy word line is connected to a second dummy memory cell in the unselected NAND string and to a second dummy memory cell in the selected NAND string;
the second dummy word line in the unselected NAND string is adjacent to the first dummy memory cell of the unselected NAND string;
the second dummy word line in the selected NAND string is adjacent to the first dummy memory cell of the selected NAND string;
threshold voltages of the second dummy memory cell of the unselected NAND string and the second dummy memory cell of the selected NAND string are higher than threshold voltages of the first dummy memory cell of the unselected NAND string and the first dummy memory cell of the selected NAND string;
the connecting comprises requesting a voltage driver of the second dummy word line to provide a first step up of a voltage on the second dummy word line concurrent with the first step up of the voltage on the first dummy word line; and
while the channel of the unselected NAND string is disconnected from the bit line, requesting the voltage driver of the second dummy word line to provide a second step up of the voltage of the second dummy word line concurrent with the second step up of the voltage on the first dummy word line.
11. A non-volatile memory device, comprising:
a selected NAND string comprising a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the selected NAND string, a selected memory cell and unselected memory cells;
an unselected NAND string comprising a drain-side select gate transistor at a drain-side of the unselected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the unselected NAND string, an unselected memory cell corresponding to the selected memory cell and other unselected memory cells;
a select gate line connected to the drain-side select gate transistor of the selected NAND string and the drain-side select gate transistor of the unselected NAND string;
a first dummy word line connected to the first dummy memory cell of the selected NAND string and the first dummy memory cell of the unselected NAND string;
a selected word line connected to the selected memory cell and the corresponding unselected memory cell;
unselected word lines connected to the unselected memory cells of the selected NAND string and the other unselected memory cells of the unselected NAND string;
a bit line connected to the selected NAND string and to the unselected NAND string; and
a control circuit, the control circuit is configured to:
provide one increase of a voltage on the select gate line, one increase of a voltage on the first dummy word line and one increase of voltages of the unselected word lines while the bit line is at a driven voltage;
subsequently provide a decrease of the voltage on the select gate line;
subsequently provide another increase of the voltage on the first dummy word line and another increase of the voltages of the unselected word lines; and
subsequently sense the selected memory cell while one or more voltages are provided on the selected word line.
12. The non-volatile memory device of claim 11, wherein:
the another increase of the voltage on the first dummy word line is after the another increase of the voltages of the unselected word lines.
13. The non-volatile memory device of claim 11, wherein:
the first dummy memory cell of the unselected NAND string comprises a charge-trapping layer.
14. The non-volatile memory device of claim 11, further comprising:
a channel in the unselected NAND string extending continuously directly under the first dummy memory cell of the unselected NAND string and directly under the drain-side select gate transistor of the unselected NAND string.
15. The non-volatile memory device of claim 11, wherein:
the select gate line extends above the first dummy word line; and
the first dummy word line extends above the selected word line and the unselected word lines.
16. A memory controller, comprising:
a storage device comprising a set of instructions; and
a processor operable to execute the set of instructions, the set of instructions comprising:
instructions to connect a channel of an unselected NAND string to a bit line while the bit line is at a driven voltage, wherein the bit line is connected to a selected NAND string, a select gate line is connected to a drain-side select gate transistor at a drain-side of the unselected NAND string and a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy word line is connected to a first dummy memory cell in the unselected NAND string adjacent to the drain-side select gate transistor of the unselected NAND string and to a first dummy memory cell in the selected NAND string adjacent to the drain-side select gate transistor of the selected NAND string, a selected word line is connected to a selected memory cell in the selected NAND string and to a corresponding unselected memory cell in the unselected NAND string, unselected word lines are connected to unselected memory cells in the selected NAND string and to corresponding unselected memory cells in the unselected NAND string, and the instructions to connect comprise instructions to step up a voltage on the select gate line, step up a voltage on the first dummy word line, and step up a voltage on the unselected word lines;
instructions to, after the connecting, disconnect the channel of the unselected NAND string from the bit line, the instructions to disconnect comprising instructions to step down the voltage on the select gate line; and
instructions to, while the channel of the unselected NAND string is disconnected from the bit line, further step up the voltage of the first dummy word line, and subsequently sense the selected memory cell while one or more voltages are provided on the selected word line.
17. The memory controller of claim 16, further comprising:
instructions to, while the channel of the unselected NAND string is disconnected from the bit line, further step up the voltage of the unselected word lines, before the sensing.
18. The memory controller of claim 16, wherein:
the further step up of the voltage of the first dummy word line is after the further step up of the voltage of the unselected word lines.
19. The memory controller of claim 16, further comprising:
instructions to ground the selected word line during the connecting; and
instructions to step up a voltage of the selected word line after the stepping down the voltage on the select gate line.
20. The memory controller of claim 16, wherein:
the further step up of the voltage of the first dummy word line is concurrent with the further step up of the voltage of the unselected word lines.