1. An image processing device comprising:
capture optics for capturing light-field information for a scene;
a display unit for providing a display of the scene to a viewer;
a tracking unit for tracking relative positions of a viewer’s head and the display and the viewer’s gaze to adjust the display based on the relative positions and to determine a region of interest on the display;
a virtual tag location unit, for determining locations to place one or more virtual tags on the region of interest, by using computational photography of the captured light-field information to determine depth information of an object in the region of interest;
a production unit for producing a mixed-reality display by combining display of the virtual tags with the display of objects in the scene.
2. The image processing device according to claim 1, further comprising a material property capturing unit for capturing a material property of the object, and a virtual tag content unit for determining the content of the virtual tag for the object, based on the captured material property.
3. The image processing device according to claim 2, wherein the material property of the object is a spectral signature.
4. The image processing device according to claim 1, wherein the virtual tag location unit determines positions for virtual tags for objects at a similar depth in the region of interest.
5. The image processing device according to claim 4, wherein the positions for the virtual tags are determined by applying a vanishing point through virtual camera positioning.
6. The image processing device according to claim 1, wherein the display is a computer-generated display which provides a three-dimensional perspective of the scene, and which is adjusted according to the relative positions of the viewer’s head and the display.
7. The image processing device according to claim 1, wherein the image data for the scene is stored in a memory without also storing the light-field information of the scene in the memory.
8. The image processing device according to claim 1, wherein the capture optics comprise multi-aperture optics.
9. The image processing device according to claim 1, wherein the capture optics comprise polydioptric optics.
10. The image processing device according to claim 1, wherein the capture optics comprise a plenoptic system.
11. A method of image processing for an image capture device comprising capture optics for capturing light-field information for a scene and a display unit, comprising:
providing a display of the scene to a viewer on the display unit;
tracking relative positions of a viewer’s head and the display and the viewer’s gaze to adjust the display based on the relative positions and to determine a region of interest on the display;
determining locations to place one or more virtual tags on the region of interest, by using computational photography of the captured light-field information to determine depth information of an object in the region of interest;
producing a mixed-reality display by combining display of the virtual tags with the display of objects in the scene.
12. The method according to claim 11, further comprising capturing a material property of the object, and determining the content of the virtual tag for the object based on the captured material property.
13. The method according to claim 12, wherein the material property of the object is a spectral signature.
14. The method according to claim 11, wherein the positions for virtual tags are determined for objects at a similar depth in the region of interest.
15. The method according to claim 14, wherein the positions for the virtual tags are determined by applying a vanishing point through virtual camera positioning.
16. The method according to claim 11, wherein the display is a computer-generated display which provides a three-dimensional perspective of the scene, and which is adjusted according to the relative positions of the viewer’s head and the display.
17. The method according to claim 11, wherein the image data for the scene is stored in a memory without also storing the light-field information of the scene in the memory.
18. The method according to claim 11, wherein the capture optics comprise multi-aperture optics.
19. The method according to claim 11, wherein the capture optics comprise polydioptric optics.
20. The method according to claim 11, wherein the capture optics comprise a plenoptic system.
21. An image processing module for an image capture device comprising capture optics for capturing light-field information for a scene and a display unit for providing a display of the scene, comprising:
a tracking module for tracking relative positions of a viewer’s head and the display and the viewer’s gaze to adjust the display based on the relative positions and to determine a region of interest on the display;
a virtual tag location module for determining locations to place one or more virtual tags on the region of interest, by using computational photography of the captured light-field information to determine depth information of an object in the region of interest;
a production module for producing a mixed-reality display by combining display of the virtual tags with the display of objects in the scene.
22. The image processing module according to claim 21, further comprising a material property capturing module for capturing a material property of the object, and a virtual tag content module for determining the content of the virtual tag for the object, based on the captured material property.
23. The image processing module according to claim 22, wherein the material property of the object is a spectral signature.
24. The image processing module according to claim 21, wherein the positions for virtual tags are determined for objects at a similar depth in the region of interest.
25. The image processing module according to claim 24, wherein the positions for the virtual tags are determined by applying a vanishing point through virtual camera positioning.
26. The image processing module according to claim 21, wherein the display is a computer-generated display which provides a three-dimensional perspective of the scene, and which is adjusted according to the relative positions of the viewer’s head and the display.
27. The image processing module according to claim 21, wherein the image data for the scene is stored in a memory without also storing the light-field information of the scene in the memory.
28. The image processing module according to claim 21, wherein the capture optics comprise multi-aperture optics.
29. The image processing module according to claim 21, wherein the capture optics comprise polydioptric optics.
30. The image processing module according to claim 21, wherein the capture optics comprise a plenoptic system.
31. A non-transitory computer-readable storage medium retrievably storing computer-executable process steps for performing a method for image processing for an image capture device comprising capture optics for capturing light-field information for a scene and a display unit for providing a display of the scene, the method comprising:
providing a display of the scene to a viewer;
tracking relative positions of a viewer’s head and the display and the viewer’s gaze to adjust the display based on the relative positions and to determine a region of interest on the display;
determining locations to place one or more virtual tags on the region of interest, by using computational photography of the captured light-field information to determine depth information of an object in the region of interest;
producing a mixed-reality display by combining display of the virtual tags with the display of objects in the scene.
32. The computer-readable storage medium according to claim 31, wherein the method further comprises capturing a material property of the object, and determining the content of the virtual tag for the object based on the captured material property.
33. The computer-readable storage medium according to claim 32, wherein the material property of the object is a spectral signature.
34. The computer-readable storage medium according to claim 31, wherein the positions for virtual tags are determined for objects at a similar depth in the region of interest.
35. The computer-readable storage medium according to claim 34, wherein the positions for the virtual tags are determined by applying a vanishing point through virtual camera positioning.
36. The computer-readable storage medium according to claim 31, wherein the display is a computer-generated display which provides a three-dimensional perspective of the scene, and which is adjusted according to the relative positions of the viewer’s head and the display.
37. The computer-readable storage medium according to claim 31, wherein the image data for the scene is stored in a memory without also storing the light-field information of the scene in the memory.
38. The computer-readable storage medium according to claim 31, wherein the capture optics comprise multi-aperture optics.
39. The computer-readable storage medium according to claim 31, wherein the capture optics comprise polydioptric optics.
40. The computer-readable storage medium according to claim 31, wherein the capture optics comprise a plenoptic system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
an isolation region formed within a semiconductor substrate;
an N-type region and a P-type region formed within the semiconductor substrate such that the N-type region and the P-type region are isolated by the isolation region;
a line electrode extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;
a PMOS transistor comprising a first gate insulating film formed over the N-type region and a first gate electrode which is the line electrode over the N-type region; and
an NMOS transistor comprising a second gate insulating film formed over the P-type region and a second gate electrode which is the line electrode over the P-type region,
wherein the line electrode comprises an electrode section (A) comprising the first gate electrode, an electrode section (B) comprising the second gate electrode and a diffusion barrier region formed for preventing contact of the electrode sections (A) and (B) over the isolation region,
wherein the diffusion barrier region contains an element different from elements in the electrode sections (A) and (B), and the electrode sections (A) and (B) are made of materials containing mutually different elements or of materials containing the same elements in a different composition, and
wherein the diffusion barrier region meets at least one of the following conditions (1) and (2):
(1) a diffusion coefficient D1 of the constituent element A\u2032 of the electrode section (A) in the diffusion barrier region is lower than an interdiffusion coefficient D2 of the constituent element A\u2032 between the electrode section (A) materials;
(2) a diffusion coefficient D3 of the constituent element B\u2032 of the electrode section (B) in the diffusion barrier region is lower than an interdiffusion coefficient D4 of the constituent element B\u2032 between the electrode section (B) materials.
2. The semiconductor device as claimed in claim 1,
wherein the electrode sections (A) and (B) as well as the diffusion barrier region are made of a silicide, and
the diffusion barrier region meets the conditions (1) and (2).
3. The semiconductor device as claimed in claim 2,
wherein the silicide constituting the diffusion barrier region is a silicide containing a metal element which becomes a diffusing species to silicon during a siliciding reaction.
4. The semiconductor device as claimed in claim 2,
wherein the silicide constituting the diffusion barrier region is a silicide of at least one metal element selected from the group consisting of Pt, Pd, Co and Ni.
5. The semiconductor device as claimed in claim 2,
wherein the electrode section (A) is made of a silicide represented by NixSi1-x (0.55\u2266x<1), and the electrode section (B) is made of a silicide represented by NixSi1-x (0<x<0.55).
6. The semiconductor device as claimed in claim 5,
wherein the electrode section (A) is made of Ni3Si or Ni2Si, and the electrode section (B) is made of NiSi or NiSi2.
7. The semiconductor device as claimed in claim 2,
wherein the silicides constituting the electrode sections (A) and (B) are dopant-containing silicides which contain dopants consisting of mutually different elements.
8. The semiconductor device as claimed in claim 7,
wherein the electrode section (A) is made of NiSi containing B, Al or In as the dopant, and the electrode section (B) is made of NiSi containing P, As or Sb as the dopant.
9. The semiconductor device as claimed in claim 2,
wherein the silicides constituting the electrode sections (A) and (B) are a refractory metal silicide.
10. The semiconductor device as claimed in claim 1,
wherein the electrode sections (A) and (B) as well as the diffusion barrier region contain the same metal element M1,
the diffusion barrier region is made of a silicide of the metal element M1, and
the metal element M1 is such an element that in a siliciding reaction of the metal element M1, silicon is a diffusing species to the metal element M1.
11. The semiconductor device as claimed in claim 10,
wherein the diffusion barrier region meets only the condition (1),
the metal element M1 is Ru, and
the electrode section (A) and the electrode section (B) are made of RuTa and Ru, respectively.
12. A semiconductor device, comprising:
an isolation region formed within a semiconductor substrate;
an N-type region and a P-type region formed within the semiconductor substrate such that the N-type region and the P-type region are isolated by the isolation region;
a line electrode extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;
a PMOS transistor comprising a first gate insulating film formed over the N-type region, and a first gate electrode which is the line electrode over the N-type region and which is made of an Ni3Si region or Ni2Si region; and
an NMOS transistor comprising a second gate insulating film formed over the P-type region, and a second gate electrode which is the line electrode over the P-type region and which is made of an NiSi region or NiSi2 region,
wherein the line electrode comprises an electrode section (A) comprising the first gate electrode formed over the N-type region, an electrode section (B) comprising the second gate electrode formed over the P-type region, and a region (C) formed over the isolation region such that the region (C) prevents contact of the electrode sections (A) and (B), the region (C) being made of a Pt silicide or Co silicide.
13. The semiconductor device as claimed in claim 12,
wherein a length of the region (C) in an extension direction of the line electrode is equal to or more than a length of the line electrode in a normal line direction of the semiconductor substrate and equal to or less than a length of the isolation region in an extension direction of the line electrode.
14. The semiconductor device as claimed in claim 1,
wherein the first and the second gate insulating films are a high-dielectric insulating film.
15. The semiconductor device as claimed in claim 1,
wherein the NMOS transistor and the PMOS transistor constitute a CMOS transistor.
16. A process for manufacturing the semiconductor device as claimed in claim 1, comprising:
preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;
forming a gate insulating film on the semiconductor substrate;
forming a polysilicon gate pattern extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;
forming a mask over the gate pattern;
removing a part of the mask formed on the gate pattern over the isolation region to expose the polysilicon;
depositing a layer of a silicide-formable metal M2 on the exposed polysilicon;
reacting the metal M2 and the polysilicon by heating to form the diffusion barrier region such that a silicide of the metal M2 is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of the metal M2 is absent over the N-type region and the P-type region, as a first siliciding step;
removing the layer of the metal M2 which is unreacted with the polysilicon during the first siliciding step; and
converting gate pattern sections over the N-type region and over the P-type region which are separated by the diffusion barrier region into the electrode sections (A) and (B) made of a silicide, respectively, as a second siliciding step.
17. The process for manufacturing the semiconductor device as claimed in claim 16,
wherein the metal M2 is Pt, and
the second siliciding step comprises:
removing the mask remaining on the gate pattern sections over the N-type and P-type regions;
depositing an Ni layer on the gate patterns;
reacting the polysilicon constituting the gate pattern sections over the N-type and the P-type regions with the Ni by heating to form NiSi regions;
removing the Ni layer unreacted with the polysilicon;
forming a mask on the NiSi region over the P-type region;
depositing an Ni layer on the NiSi region over the N-type region;
reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni3Si;
removing the Ni layer unreacted with the NiSi; and
removing the mask formed on the NiSi region over the P-type region.
18. The process for manufacturing the semiconductor device as claimed in claim 16,
wherein in forming the gate pattern, dopant-containing polysilicons are formed such that the dopant-containing polysilicons over the N-type and the P-type regions contain dopants consisting of different elements, as the polysilicon,
the metal M2 is Pt; and
the second siliciding step comprises:
removing the mask remaining on the gate pattern sections over the N-type and P-type regions;
depositing an Ni layer on the gate patterns;
reacting dopant-containing polysilicons constituting the gate pattern sections over the N-type and the P-type regions with the Ni by heating, respectively, to form dopant-containing NiSi regions; and
removing the Ni layer unreacted with the dopant-containing polysilicon.
19. The process for manufacturing the semiconductor device as claimed in claim 16,
wherein the metal M2 is Co, and
the second siliciding step comprises:
removing the mask formed on the gate pattern section over the N-type region;
depositing an Mo layer on the gate pattern section over the N-type region;
reacting the Mo with the polysilicon constituting the gate pattern section over the N-type region by heating to form MoSi2;
removing the Mo layer unreacted with the polysilicon;
removing the mask formed on the gate pattern section over the P-type region;
depositing a Hf layer on the gate pattern section over the P-type region;
reacting the Hf with the polysilicon constituting the gate pattern section over the P-type region by heating to form HfSi; and
removing the Hf layer unreacted with the polysilicon.
20. A process for manufacturing the semiconductor device as claimed in claim 1, comprising:
preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;
forming a gate insulating film on the semiconductor substrate;
forming a polysilicon gate pattern extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;
forming a mask over the gate pattern;
removing the mask formed on gate pattern sections over the N-type and the P-type regions to expose the polysilicon;
depositing a layer of a silicide-formable metal M3 on the exposed polysilicon;
reacting the metal M3 with the exposed polysilicon by heating to converting at least part of the gate pattern sections over the N-type and the P-type regions into metal M3 silicide regions such that the gate pattern sections of the N-type and the P-type regions are not mutually communicated over the isolation region, as a third siliciding step;
removing the layer of the metal M3 unreacted with the polysilicon during the third siliciding step;
removing the mask remaining on the gate pattern over the isolation region to expose the polysilicon;
depositing a layer of a silicide-formable metal M4 on the exposed polysilicon;
reacting the metal M4 with the exposed polysilicon by heating to form the diffusion barrier region such that a silicide of the metal M4 is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of the metal M4 is absent over the N-type region and the P-type region, as a fourth siliciding step;
removing the layer of the metal M4 unreacted with the polysilicon during the fourth siliciding step; and
converting the metal M3 silicide regions over the N-type and the P-type regions into the electrode sections (A) and (B), respectively, as a fifth siliciding step.
21. The process for manufacturing the semiconductor device as claimed in claim 20,
wherein the third siliciding step is reacting the metal M3 with the upper part of the polysilicon to form an Ni2Si region and to leave the unreacted polysilicon in the lower part of the Ni2Si region,
the metal M4 is Pt, and
the fifth siliciding step comprises:
reacting the Ni2Si constituting the Ni2Si region with the polysilicon remaining in the lower part of the Ni2Si region by heating to form an NiSi region;
forming a mask on the NiSi region over the P-type region;
depositing an Ni layer on the NiSi region over the N-type region;
reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni3Si;
removing the Ni layer unreacted with the NiSi; and
removing the mask formed on the NiSi region over the P-type region.
22. The process for manufacturing the semiconductor device as claimed in claim 20,
wherein the third siliciding step is reacting the metal M3 with all the polysilicon constituting the gate pattern sections over the N-type and the P-type regions to form an NiSi region,
the metal M4 is Pt, and
the fifth siliciding step comprises:
forming a mask on the NiSi region over the P-type region;
depositing an Ni layer on the NiSi region over the N-type region;
reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni3Si;
removing the Ni layer unreacted with the NiSi; and
removing the mask formed on the NiSi region over the P-type region.
23. The process for manufacturing the semiconductor device as claimed in claim 20,
wherein in forming the gate pattern, dopant-containing polysilicons are formed such that dopant-containing polysilicons over the N-type and the P-type regions contain dopants of different elements, as the polysilicon,
the third siliciding step is reacting the metal M3 with the upper part of the dopant-containing polysilicon to form a dopant-containing Ni2Si region and to leave the unreacted dopant-containing polysilicon in the lower part of the dopant-containing Ni2Si region,
the metal M4 is Pt, and
the fifth siliciding step comprises the step of reacting the dopant-containing Ni2Si constituting the dopant-containing Ni2Si region with the dopant-containing polysilicon remaining in the lower part of the dopant-containing Ni2Si region by heating to form a dopant-containing NiSi.
24. A process for manufacturing the semiconductor device as claimed in claim 1, comprising:
preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;
forming a gate insulating film on the semiconductor substrate;
forming a gate pattern made of Ru extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;
forming a mask over the gate pattern;
removing a part of the mask formed on the gate pattern over the isolation region to expose the Ru;
depositing a silicon layer on the exposed Ru;
reacting the Ru with the silicon by heating to form the diffusion barrier region such that a silicide of the Ru is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of Ru is absent over the N-type region and the P-type region, as a sixth siliciding step;
removing the silicon layer unreacted with the Ru in the sixth siliciding step;
removing the mask remaining on the gate pattern section over the N-type region;
depositing a Ta layer on the gate pattern section over the N-type region;
reacting the Ru constituting the gate pattern section over the N-type region with the Ta by heating to form RuTa;
removing the Ta layer unreacted with the Ru; and
removing the mask remaining on the gate pattern section over the P-type region.