1. A method for an orthogonal frequency division multiplexing multipoint-to-point communications system, the method comprising:
establishing communication between a first remote unit of a plurality of remote units and a host unit, the plurality of remote units communicatively coupled to the host unit in a multipoint-to-point configuration using orthogonal frequency division multiplexing; and
adjusting a round trip path delay associated with the first remote unit.
2. The method of claim 1 further comprising:
transmitting up to a plurality of tones from the first remote unit, the up to a plurality of tones modulated with upstream information using orthogonal frequency division multiplexing; and
adjusting at least one characteristic of the plurality of tones such that when any tones are transmitted from the first remote unit and at least one other remote unit of the plurality of remote units, the orthogonality of the tones when received at the host unit is improved.
3. The method of claim 2, wherein adjusting at least one characteristic of the plurality of tones comprises adjusting at least one of a carrier frequency, a carrier amplitude, and a phase.
4. The method of claim 1 further comprising:
receiving up to a plurality of tones from the first remote unit, the up to a plurality of tones modulated with upstream information using orthogonal frequency division multiplexing; and
adjusting at least one characteristic of the plurality of tones such that when any tones are transmitted from the first remote unit and at least one other remote unit of the plurality of remote units, the orthogonality of the tones when received at the host unit is improved.
5. The method of claim 4, wherein adjusting at least one characteristic of the plurality of tones comprises adjusting at least one of a carrier frequency, a carrier amplitude, and a phase.
6. The method of claim 1 further comprising:
sending a first signal on a first tone of the plurality of tones, the first signal instructing the first remote unit to transmit a second signal onto a second tone of the plurality of tones;
estimating a round trip delay associated with the first remote unit based on the second signal; and
sending a third signal instructing the first remote unit to adjust transmission of data based on the estimated round trip delay.
7. The method of claim 1 further comprising:
estimating a round trip path delay time for the first remote unit that will align multiframes received at the host unit from the first remote unit with any other multiframes received at the host unit from the plurality of remote units.
8. The method of claim 1 further comprising:
receiving a ranging signal at the host unit, the ranging signal transmitted from the first remote unit;
estimating a round trip path delay based on the ranging signal; and
sending a path delay adjustment value to the first remote unit to assist in achieving orthogonal frequency division multiplexing for subsequent transmissions from the plurality of remote units to the host unit.
9. A method for an orthogonal frequency division multiplexing multipoint-to-point communications system, the method comprising:
receiving an orthogonal frequency division multiplexing waveform at a multipoint-to-point host unit, the orthogonal frequency division multiplexing waveform comprising a plurality of tones transmitted by a plurality of remote units;
receiving at least one ranging signal at the multipoint-to-point host unit, the at least one ranging signal transmitted from at least one of the plurality of remote units;
estimating at least one round trip path delay based on the at least one ranging signal; and
adjusting the at least one round trip path delay between the multipoint-to-point host unit and the at least one of the plurality of remote units.
10. The method of claim 9, wherein receiving the orthogonal frequency division multiplexing waveform at the multipoint-to-point host unit further comprises receiving a plurality of tones from more than one of the plurality of remote units.
11. The method of claim 9, wherein receiving the orthogonal frequency division multiplexing waveform at the multipoint-to-point host unit further comprises receiving a plurality of tones from one of the plurality of remote units.
12. The method of claim 9, wherein adjusting the at least one round trip path delay further comprises adjusting each of the plurality of remote units to achieve alignment within a predefined margin at the host unit of any upstream transmissions by the plurality of remote units.
13. A method for an orthogonal frequency division multiplexing multipoint-to-point communications system, the method comprising:
establishing communication between a first remote unit of a plurality of remote units and a host unit, the plurality of remote units communicatively coupled to the host unit in a multipoint-to-point configuration;
receiving a round trip delay adjustment based on an estimated round trip delay period between the first remote unit and the host unit; and
delaying transmission of up to a plurality of tones from the first remote unit based on the round trip delay adjustment, the up to a plurality of tones modulated with upstream information using orthogonal frequency division multiplexing.
14. The method of claim 13 further comprising:
receiving up to a plurality of tones from the host unit; and
receiving an instruction to delay transmission based on an estimated round trip delay associated with the first remote unit.
15. The method of claim 13 further comprising:
transmitting a ranging signal from the first remote unit to the host unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A system for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, said system comprising:
a plurality of column switches adapted for coupling the plurality of columns of said LCD to an output voltage;
a plurality of row switches adapted for selectively coupling the plurality of columns to the pixels of said LCD; and
logic circuitry coupled to the plurality of column switches and the plurality of row switches, said logic circuitry adapted to send a control signal to the plurality of column switches to couple said columns to a fixed voltage prior to the writing of each row, thereby charging said columns prior to the writing of each row.
2. A system for writing a video frame in a liquid crystal display (LCD) according to claim 1, wherein the logic circuitry includes a column control logic circuit coupled to the plurality of column switches and a row control logic circuit coupled to the plurality of row switches.
3. A system for writing a video frame in a liquid crystal display (LCD) according to claim 1, wherein the logic circuitry is coupled to at least one digital-to-analog converter (DAC), which outputs the output voltage, and said logic circuitry commands said at least one DAC to output a desired video voltage.
4. A system for writing a video frame in a liquid crystal display (LCD) according to claim 3, wherein the logic circuitry commands said at least one DAC to output the fixed voltage.
5. A system for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, said system comprising:
a plurality of column switches adapted for coupling the plurality of columns of said LCD to an output voltage;
a plurality of secondary column switches adapted for coupling at least one of the plurality of columns to a fixed voltage;
a plurality of row switches adapted for selectively coupling the plurality of columns to the pixels of said LCD; and
logic circuitry coupled to the plurality of primary and secondary column switches and the plurality of row switches, said logic circuitry adapted to send a control signal to the at least one secondary column switch to couple at least one of the plurality of columns to the fixed voltage thereby charging said at least one column prior to the writing of each row.
6. A system for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, said system comprising:
a plurality of column switches adapted for coupling the plurality of columns of said LCD to an output voltage;
a plurality of row switches adapted for selectively coupling the plurality of columns to the pixels of said LCD; and
logic circuitry coupled to the plurality of column switches and the plurality of row switches, said logic circuitry adapted to send a control signal to the plurality of column switches to couple said columns to each other to thereby equalize one or more voltages stored on said columns prior to the writing of each row.
7. A system for writing a video frame in a liquid crystal display (LCD) according to claim 6, wherein the logic circuitry includes a column control logic circuit coupled to the plurality of column switches and a row control logic circuit coupled to the plurality of row switches.
8. A system for writing a video frame in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, said system comprising:
a plurality of primary column switches adapted for coupling the plurality of columns of said LCD to an output voltage;
a plurality of secondary column switches adapted for coupling at least one of the plurality of columns of said LCD to a fixed voltage;
a plurality of row switches adapted for selectively coupling the plurality of columns to the pixels of said LCD; and
logic circuitry coupled to the plurality of primary and secondary column switches and the plurality of row switches, said logic circuitry adapted to send a control signal to one primary column switch to couple its associated column to a desired video voltage and another control signal to a secondary column switch in a successive column so as to couple the successive column to the fixed voltage to thereby charge said successive column while the preceding column is being charged to the desired video voltage.
9. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry includes a column control logic circuit coupled to the plurality of primary and secondary column switches and a row control logic circuit coupled to the plurality of row switches.
10. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry is adapted to send a control signal to the secondary column switches in the successive two or more columns to couple said two or more successive columns to the fixed voltage while the preceding column is being charged to the desired video voltage.
11. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry is adapted to send a control signal to the primary column switch to couple the successive column to a desired video voltage and send a control signal to a secondary column switch corresponding to the next successive column to couple said next successive column to the fixed voltage, so that as the successive column is being charged to its desired video voltage the next successive column is being charged to the fixed voltage.
12. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry is adapted to send control signals to the primary and secondary column switches and the row switches so that the sequence of charging one column capacitor to a desired video voltage while the successive column capacitor is being charged to a fixed voltage is repeated until all of the pixels in a given row have been written, and said sequence is again repeated for each successive row until all of the rows in the matrix have been written.
13. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry is coupled to at least one digital-to-analog converter (DAC), which outputs the output voltage, and said logic circuitry commands said at least one DAC to output the desired video voltage.
14. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the logic circuitry is coupled to at least one digital-to-analog converter (DAC), which outputs the output voltage, and said logic circuitry commands said at least one DAC to output the fixed voltage.
15. A system for writing a video frame in a liquid crystal display (LCD) according to claim 8, wherein the fixed voltage is generated by a voltage supply independent from the voltage supply that generates the desired video voltage.
16. A method for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, wherein each column has an associated capacitor and each pixel has an associated capacitor, said method comprising the step of charging the column capacitors to a fixed voltage prior to writing each row.
17. A method for writing a video frame in a liquid crystal display (LCD) according to claim 16, wherein the column capacitors are charged to a fixed voltage by coupling them to an analog voltage driven to a selected preferred voltage under the command of a logic circuit.
18. A method for writing a video frame in a liquid crystal display (LCD) according to claim 16, wherein the column capacitors are charged to a fixed voltage by coupling them to a voltage supply driven to a selected preferred voltage.
19. A method for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, wherein each column has an associated capacitor and each pixel has an associated capacitor, said method comprising the step of coupling the column capacitors together prior to writing each row, so that the voltage stored on the column capacitors is equalized to an average value prior to writing each row.
20. A method for writing a video frame row by row in a liquid crystal display (LCD) having a matrix of liquid crystal pixels arranged in a plurality of columns and a plurality of rows, wherein each column has an associated capacitor and each pixel has an associated capacitor, said method comprising the step of charging a column capacitor to a desired video voltage while charging a successive column capacitor to a fixed voltage during the writing of each row.
21. A method for writing a video frame in a liquid crystal display (LCD) according to claim 20, wherein the step is performed by charging two or more successive column capacitors to a fixed voltage while charging the column capacitor to the desired video voltage.
22. A method for writing a video frame in a liquid crystal display (LCD) according to claim 20, wherein after the successive column capacitor is charged to the fixed voltage it is charged to a desired video voltage and at the same time the next successive column capacitor is charged to the fixed voltage.
23. A method for writing a video frame in a liquid crystal display (LCD) according to claim 20, wherein the sequence of charging one column capacitor to a desired video voltage while the successive column capacitor is being charged to a fixed voltage is repeated until all of the pixels in a given row have been written, and said sequence is again repeated for each successive row until all of the rows in the matrix have been written.
24. A method for writing a video frame in a liquid crystal display (LCD) according to claim 20, wherein the column capacitor is charged to the fixed voltage by coupling it to an analog voltage driven to a selected preferred voltage under the command of a logic circuit.
25. A method for writing a video frame in a liquid crystal display (LCD) according to claim 20, wherein the column capacitor is charged to the fixed voltage by coupling it to a voltage supply driven to a selected preferred voltage.