1. A system for managing one or more power outlets selected from each of a one or more power distribution units, wherein each of the one or more power distribution units includes means to individually manage each selected power outlet comprising the power distribution unit and further includes an input terminal for receiving electronic signals, thereby forming a virtual power distribution unit, the system comprising:
a controller comprising:
an electronic data storage device for storing data corresponding to each of the power outlets, and
means to send signals to an output terminal, wherein each signal corresponds to a portion of the data, said portion corresponding to a certain power outlet; and
an electronic path for carrying the signal from the output terminal of the controller to the input terminal of each power distribution unit.
2. The system according to claim 1, wherein the storage device is semiconductor memory.
3. The system according to claim 1, wherein the storage device is a hard disc drive.
4. The system according to claim 1, wherein the storage device is a removable floppy disc.
5. The system according to claim 1, wherein the storage device is a compact disc.
6. The system according to claim 1, wherein the means for providing an output signal to the output terminal comprises:
a storage device for storing the data;
a storage device for storing program instructions; and
a microprocessor for executing the program instructions.
7. The system according to claim 6, wherein the device for storing the data is semiconductor memory.
8. The system according to claim 6, wherein the device for storing program instructions is semiconductor memory.
9. The system according to claim 1, wherein the electronic path comprises a local area network.
10. The system according to claim 1 further comprising an input terminal to the controller and an output terminal from at least one of the one or more power distribution units.
11. The system according to claim 10, wherein the electronic path includes a connection to the internet.
12. The system according to claim 10, wherein the electronic data path further includes a gateway.
13. The system according to claim 10, wherein the electronic data path further includes a server.
14. A method for managing one or more power outlets selected from each of a one or more power distribution units to form a virtual power distribution unit, the method comprising the steps of:
a. receiving a command;
b. creating a list of power outlets, the power outlets selected according to a meaning of the command, wherein each power outlet has a unique identification symbol, each identification symbol corresponding to a unique identification symbol of a virtual power outlet associated with a certain virtual power distribution unit;
c. performing an operation responsive to the command on a database record, wherein the database record corresponds to a certain power outlet from the list of power outlets; and
d. repeating the method from step \u201cc.\u201d for each database record corresponding to each power outlet on the list of power outlets until the command has been responded to for all power outlets on the list of power outlets.
15. The method according to claim 14, wherein the meaning of the command is to turn a power outlet ON.
16. The method according to claim 14, wherein the meaning of the command is to turn a power outlet OFF.
17. The method according to claim 14, wherein the meaning of the command is to request data from the power outlet.
18. The method according to claim 14, wherein the meaning of the command is to associate a selected power outlet with a selected virtual power outlet of a given virtual power distribution unit.
19. The method according to claim 14, wherein the meaning of the command is to disassociate a selected power outlet from a selected virtual power outlet of a given virtual power distribution unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising: a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that is segregated on top of a silicide; a gate dielectric on the semiconductor substrate; a gate on the gate dielectric; sourcedrain junctions in the semiconductor substrate; a silicide on the sourcedrain junctions; segregated dopant on the top surface of the silicide; an insulating layer of oxidized dopant on the top surface of the segregated dopant above the silicide; an interlayer dielectric above the semiconductor substrate; and contacts and connection points in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide, wherein the contacts and connection points further comprise closed connection points and open connection points.
2. The integrated circuit as claimed in claim 1 further comprising:
at least a portion of the insulating layer of oxidized dopant being configured as anti-fuse programmable elements; and
an electrical closed circuit through at least one of the anti-fuse programmable elements.
3. The integrated circuit as claimed in claim 1 wherein the semiconductor substrate is a silicon substrate that is doped with a set concentration of arsenic dopant to form an n-type semiconductor region.
4. The integrated circuit as claimed in claim 1 wherein the contacts in the interlayer dielectric to the insulating oxide layer above the silicide use materials selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.
5. An integrated circuit comprising: a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that is segregated on top of a silicide; a gate dielectric on the semiconductor substrate; a gate on the gate dielectric; sourcedrain junctions in the semiconductor substrate and low and high concentration regions therein of the oxidizable dopant; a silicide on the sourcedrain junctions and on the gate; segregated dopant from the high concentration regions on the top surface of the silicide on the sourcedrain junctions; an insulating layer of oxidized dopant on the top surface of the segregated dopant above the silicide; an interlayer dielectric above the semiconductor substrate; and contacts and connection points in the interlayer dielectric to the insulating layer of oxidized dopant above the high concentration regions, and to the silicide above the low concentration regions, wherein the contacts and connection points further comprise closed connection points above the low concentration regions and open connection points above the high concentration regions.
6. The integrated circuit as claimed in claim 5 further comprising:
at least a portion of the insulating layer of oxidized dopant being configured as anti-fuse programmable elements; and
an electrical closed circuit through at least one of the anti-fuse programmable elements.
7. The integrated circuit as claimed in claim 5 wherein the semiconductor substrate is a silicon substrate that is doped with a set concentration of arsenic dopant to form an n-type semiconductor region.
8. The integrated circuit as claimed in claim 5 wherein the contacts to the insulating layer of oxidized dopant and to the silicide further comprise cores within a barrier metal formed of materials selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.