1. A shift register, comprising:
cascade-connected unit circuits, each of which includes a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, wherein
the thin-film transistor is a bottom gate thin-film transistor which includes a comb-shaped sourcedrain structure,
the source electrode includes a source trunk portion and a plurality of source branch portions which are branched from the source trunk portion and which correspond to teeth of a comb,
the drain electrode includes a drain trunk portion and a plurality of drain branch portions which are branched from the drain trunk portion and which correspond to teeth of a comb,
the source electrode and the drain electrode face each other,
the plurality of source branch portions and the plurality of drain branch portions are alternatingly arranged,
the gate electrode is provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode, and
the at least one of the cut and the opening faces at least one of the plurality of source branch portions and the plurality of drain branch portions.
2. The shift register according to claim 1,
wherein the cascade-connected unit circuits each include a clock terminal into which a clock signal is fed and an output terminal through which an output signal is sent out, and
the shift register includes an output transistor disposed between the clock terminal and the output terminal, the output transistor switching passage and cutout of the clock signal according to a gate potential.
3. The shift register according to claim 2,
wherein the thin-film transistor is the output transistor, and
the at least one of a cut and an opening is defined in a region overlapping with one electrode connected to the clock terminal, the one electrode being selected from the source electrode and the drain electrode.
4. The shift register according to claim 3,
wherein the gate electrode is provided with no cut and no opening in a region overlapping with one electrode selected from the source electrode and the drain electrode, the one electrode being connected to the output terminal.
5. The shift register according to claim 2,
wherein the thin-film transistor is a transistor arranged to apply a low level voltage to the output terminal at times other than a time of sending of the output signal, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
6. The shift register according to claim 2,
wherein the thin-film transistor is a transistor arranged to apply a low level voltage to a node connected to a gate of the output transistor during a period other than a period for turning the output transistor ON, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
7. The shift register according to claim 2,
wherein the shift register includes a first transistor in which source or drain is connected to the gate of the output transistor,
the thin-film transistor is a transistor arranged to apply a low level voltage to a node connected to a gate of the first transistor during a period for turning the output transistor ON, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
8. The shift register according to claim 2,
wherein the cascade-connected unit circuits each include an input terminal into which a start pulse is fed or an output signal is fed from the previous circuit,
the thin-film transistor is a transistor in which one of a source and a drain is connected to the gate of the output transistor and a gate and the other of the source and the drain are connected to the input terminal,
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
9. The shift register according to claim 1,
wherein the thin-film transistor is made of amorphous silicon.
10. A display device, comprising:
a plurality of pixel circuits arranged in a matrix pattern; and
a driver including the shift register according to claim 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for receiving a FEC frame for variable-length frame transmission in a TDMA system, the apparatus comprising:
a first receiver determining whether a received frame is a FEC encoded frame, wherein when the received frame is a FEC encoded frame having a predetermined number of message blocks and parities equal in number to the message blocks sequentially, the first receiver divides the FEC encoded frame into the message blocks and parities after removing a FEC frame identifier from the FEC encoded frame, the first receiver includes a data buffer and a parity buffer respectively storing the message blocks and the parities;
a Reed-Solomon decoder receiving the FEC encoded frame from the first receiver, and Reed-Solomon decoding the FEC encoded frame in a same processing time regardless of the length of the FEC encoded frame, wherein the Reed-Solomon decoder calculates an error magnitude polynomial to determine an error value of the FEC encoded frame, the Reed-Solomon decoder buffers an error magnitude polynomial in a first buffer and an error location polynomial in a second buffer to determine an error value of the FEC encoded frame, the Reed-Solomon decoder further comprising:
a syndrome calculator calculating a syndrome for each of the codewords,
a codeword counter counting the length of the codewords,
the error location polynomial generator receiving the syndrome calculated by the syndrome calculator, and generating an error location polynomial and the error magnitude polynomial using a recursive modified Euclid algorithm,
an error location detection unit searching for a location of the error of the codeword using the Chien algorithm based on initial values of the lengths of codewords,
an error magnitude detection unit searching for the magnitude of the error of the codeword using the Forney algorithm based on the initial values, and
a memory comprising a first queue storing the error location polynomial output from the error location polynomial generator, and a second queue storing the error magnitude polynomial output from the error location polynomial generator, and storing the error location polynomial and the error magnitude polynomial until the error location detection unit and the error magnitude detection unit complete to process a previous codeword for output;
a matching delay receiving an input FEC unencoded frame from the first receiver, and delaying the FEC unencoded frame by the time required to decode a FEC encoded frame, or delaying a FEC frame identifier by the time required to decode a FEC encoded frame; and
a frame recombiner adding a Reed-Solomon decoded codeword to the FEC frame identifier in response to the output from the matching delay to form an original FEC frame.
2. The apparatus of claim 1, wherein the data buffer and the parity buffer are elastic buffers that provide each of the received frames with the same delay time.
3. The apparatus of claim 1, wherein the Reed-Solomon decoder further comprises:
a look-up table storing the initial values each in the error location detection unit and the error magnitude detection unit, and outputting the initial values in the codeword counter using them as addresses for outputting to the error location detection unit and the error magnitude detection unit.
4. The apparatus of claim 3, wherein the memory further comprises a third queue queuing the codeword.
5. The apparatus of claim 1, further comprising:
a buffer that delays the received frame by a time required to perform the Reed-Solomon decoding, resulting in an error corrected frame; and
wherein the frame recombiner zero-pads a position in the error corrected frame corresponding to a parity storing space.
6. A method of receiving a FEC frame structure for variable-length frame transmission in a TDMA system, the method comprising:
determining whether a received frame is a FEC encoded frame;
when the received frame is determined to be a FEC encoded frame having a predetermined number of message blocks and parities equal in number to the message blocks sequentially, removing a FEC frame identifier from the FEC encoded frame and dividing the FEC encoded frame into the message blocks and parities;
Reed-Solomon decoding the FEC encoded frame with a fixed processing time regardless of its length, wherein the Reed-Solomon decoding comprises buffering an error magnitude polynomial and an error location polynomial to determine an error value of the FEC encoded frame, wherein the Reed-Solomon decoding comprises:
buffering the divided message blocks and parities for the same time for every frame,
calculating a syndrome of codewords,
counting the length of the codewords,
generating an error location polynomial and the error magnitude polynomial using a recursive modified Euclid algorithm on the syndrome, and
queuing the error location polynomial and the error magnitude polynomial until generating the error location polynomial and the error magnitude polynomial with respect to a previous codeword,
determining a location of an error of the codeword using the Chien algorithm based on initial values selected from a predetermined look-up table according to the length of the codeword; and
determining a magnitude of the error of the codeword using the Forney algorithm based on the initial values;
delaying the received frame by the time required to decode a FEC encoded frame when the received frame is determined to be a FEC unencoded frame, or delaying a FEC frame identifier by the time required to perform the Reed-Solomon decoding; and
adding a Reed-Solomon decoded codeword and the delayed FEC frame identifier in response to delaying the FEC frame identifier to form an original FEC frame.
7. The method of claim 6, wherein the determining location of the error of the codeword further comprises:
configuring the look-up table storing the initial values each in order for the error location detection and the error magnitude detection, and using the length of the codeword as an address in order to generate the initial values.
8. The method of claim 6, wherein the delaying the FEC frame identifier comprises:
zero-padding a position in the frame corresponding to a parity storing space.