1) A method for reducing soft errors in logic comprising:
a) obtaining a first delayed data signal;
b) obtaining a second delayed data signal;
c) applying a data signal from a logic circuit, the delayed data signals, and a clock signal to a triple redundant memory element;
d) such that the time delay of the first delayed data signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
e) such that the time delay of the second delayed data signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
2) The method as in claim 1 wherein the delayed data signals are obtained by fabricating a chain of inverters in series.
3) The method as in claim 1 wherein the delayed data signals are obtained by fabricating one or more capacitors and one or more resistors in a pi-network.
4) The method as in claim 1 wherein the triple redundant memory element comprises:
a) three memory elements;
b) a majority voting logic circuit;
c) wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
d) wherein the clock signal is connected to all three memory elements;
e) wherein the data signal is connected to the first memory element;
f) wherein the first delayed data signal is connected to the third memory element;
g) wherein the second delayed data signal is connected to the second memory element.
5) The method as in claim 4 wherein the memory elements are DRAMs.
6) The method as in claim 4 wherein the memory elements are SRAMs.
7) The method as in claim 4 wherein the memory elements are D-type flip-flops.
8) The method as in claim 4 wherein the memory elements are pulsed latches.
9) The method as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input NANDs;
b) one three-input NAND;
c) wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
10) The method as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input ANDs;
b) one three-input OR;
c) wherein each output from the three two-input ANDs are connected to an input of the three-input OR.
11) A circuit for reducing soft errors in logic comprising:
a) a first delay element;
b) a second delay element;
c) a triple redundant memory element;
d) wherein a data signal from a logic circuit is applied to the first delay element, the second delay element, and to a triple redundant memory element;
e) wherein an output from the first delay element is connected to the triple redundant memory element;
f) wherein an output from the second delay element is connected to the triple redundant memory element;
g) wherein a clock signal is applied to the triple redundant memory element;
h) such that the time delay of the first delayed data signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
i) such that the time delay of the second delayed data signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
12) The circuit as in claim 11 wherein the delay elements are a chain of inverters in series.
13) The circuit as in claim 11 wherein the delay elements are one or more capacitors and one or more resistors in a pi-network.
14) The circuit as in claim 11 wherein the triple redundant memory element comprises:
a) three memory elements;
b) a majority voting logic circuit;
c) wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
d) wherein the clock signal is connected to all three memory elements;
e) wherein the data signal is connected to the first memory element;
f) wherein the first delayed data signal is connected to the third memory element;
g) wherein the second delayed data signal is connected to the second memory element.
15) The circuit as in claim 14 wherein the memory elements are DRAMs.
16) The circuit as in claim 14 wherein the memory elements are SRAMs.
17) The circuit as in claim 14 wherein the memory elements are D-type flip-flops.
18) The circuit as in claim 14 wherein the memory elements are pulsed latches.
19) The circuit as in claim 14 wherein the majority voting logic circuit comprises:
a) three two-input NANDs;
b) one three-input NAND;
c) wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
20) The circuit as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input ANDs;
b) one three-input OR;
c) wherein each output from the three two-input ANDs are connected to an input of the three-input OR.
21) A circuit for reducing soft errors in logic comprising:
a) a first means for delaying a data signal;
b) a second means for delaying a data signal;
c) a means for storing a logical value in three distinct locations;
d) a means for outputting a same logical value as is present on two of the three inputs;
e) wherein a data signal is applied to the first means for delaying a data signal, the second means for delaying a data signal, and to a first location of the means for storing a logical value in three distinct locations;
f) wherein a clock signal is applied to the means for storing a logical value in three distinct locations;
g) such that the time delay through the first means for delaying a data signal is greater than the pulse width of a soft error event occurring in the logic circuit;
h) such that the time delay through the second means for delaying a data signal is greater than half the pulse width of a soft error event occurring in the logic circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resonator of a hybrid laser diode comprising:
a substrate including a semiconductor layer where a hybrid waveguide, a multi-mode waveguide, and a single mode waveguide are connected in series;
a compound semiconductor waveguide, provided on the hybrid waveguide of the semiconductor layer, having a tapered coupling structure at one end of the compound semiconductor waveguide, the tapered coupling structure overlapping the multi-mode waveguide partially; and
a reflection part provided on one end of the single mode waveguide,
wherein the multi-mode waveguide has a narrower width than the hybrid waveguide and the single mode waveguide has a narrower width than the multi-mode waveguide.
2. The resonator of claim 1, wherein the compound semiconductor waveguide has a width of more than about 5 \u03bcm.
3. The resonator of claim 1, wherein the compound semiconductor waveguide comprises a Group III-V compound semiconductor.
4. The resonator of claim 1, wherein the substrate is a silicon on insulator (SOI) substrate including an underlying semiconductor layer, an insulation layer on the underlying semiconductor layer, and the semiconductor layer on the insulation layer.
5. The resonator of claim 4, wherein the compound semiconductor waveguide is formed by bonding with the semiconductor layer of the substrate.
6. The resonator of claim 1, further comprising a mode selecting unit provided between the multi-mode waveguide and the single mode waveguide.
7. The resonator of claim 6, wherein the mode selecting unit is a multi-mode interference waveguide.
8. The resonator of claim 1, wherein the reflection part uses a distributed Bragg reflector or a facet reflection, the disturbed Bragg reflector being a waveguide with diffraction gratings.
9. The resonator of claim 1, wherein the hybrid waveguide, the multi-mode waveguide, and the single mode waveguide are connected in series through respective transition area waveguides therebetween.
10. The resonator of claim 9, wherein the transition area waveguide has a width that becomes narrower when it approaches from the hybrid waveguide to the multi-mode waveguide and from the multi-mode waveguide to the single mode waveguide.