1-14. (canceled)
15. A transmission device (1) with power branching, the transmission device (1) comprising:
a first power branch (3) and a second power branch (5),
with a transmission arrangement (9) in a form of a planetary gear system for summing parts of applied torque that are transmittable by way of the first and the second power branches (3, 5),
a hydrostatic device (4) having a first hydraulic unit (10) and a second hydraulic unit (11), the first hydraulic unit (10) being connected to a second hydrostatic shaft (29) and the second hydraulic unit (11) being connected to a first hydrostatic shaft (28) such that, in each case, first, second and third driving ranges, for forward and reverse driving, are provided which can be shifted, respectively, between by at least one shifting element (K1 to K3) that has to be disengaged and at least one shifting element (K1 to K3) that has to be engaged, and each of the shifting elements (K1 to K3) being arranged on a separate countershaft (14, 15 16),
the planetary gear system comprising a first and a second sun gear (21, 22) which engage with common double planetary gearwheels (23), a ring gear (25) and a planetary carrier (24) such that the second sun gear (22) being connected to the second hydrostatic shaft (29) and the ring gear (25) being connected, by way of a fixed wheel (26) and a further fixed wheel (27), to the first hydrostatic shaft (28),
in the first and the third driving ranges, the power of the first and the second power branches (3, 5) being summed by the first hydrostatic shaft (28) connected to the second hydraulic unit (11) and the further fixed wheel and an other fixed wheel (27, 36) being arranged on the first hydrostatic shaft (28) such that a shifting element half of a first shifting element (K1), by which the first driving range is obtained in the engaged operating condition of the first shifting element (K1), being functionally connected by way of a gearwheel (33; 43) of the countershaft (14) to the transmission output shaft (8) and another shifting element half, of the first shifting element (K1), being functionally connected by way of a further gearwheel (35) of the countershaft (14) to the first hydrostatic shaft (28) connected to the hydrostatic device (4), and
such that either an inner disk carrier or an outer disk carrier of the first shifting element (K1) being connected to the countershaft (14) and either the outer disk carrier or the inner disk carrier being connected to a gearwheel (35 or 33) which is coupled by the first shifting element (K1) to the associated countershaft (14),
and such that the gearwheel (35 or 33) that is connectable, in a rotationally fixed manner, by the first shifting element (K1) to the associated countershaft (14) being functionally connected to the transmission output shaft (8) and the fixed wheel (33 or 35 or 43) of the countershaft (14) meshing with a fixed wheel (36) of the first hydrostatic shaft (28) associated with the hydrostatic device (4).
16. The transmission device according to claim 15, wherein for the power branching and for summing the parts of the applied torque, which can be transmitted by the power branches, the transmission arrangement (9) in the form of a planetary gear system is provided, which comprises two sun gears (21, 22) that engage with common double planetary gearwheels (23) which, in turn, mesh with the ring gear (25).
17. The transmission device according to claim 15, wherein the gearwheel (35 or 33) which is connectable, in a rotationally fixed manner, by the first shifting element (K1) to the associated countershaft (14) meshes with a fixed wheel (36) of the first hydrostatic shaft (28) associated with the hydrostatic device (4), and a fixed wheel (33 or 35 or 43) of the countershaft (14) is functionally connected to the transmission output shaft (8).
18. The transmission device according to claim 15, wherein a loose wheel (31) which is connectable in a rotationally fixed manner to the associated countershaft (15) by a second shifting element (K2), by which the second driving range can be obtained when the second shifting element (K2) is in an engaged operating condition, meshes with a fixed wheel (30) connected in a rotationally fixed manner to the first sun gear (21) of the transmission arrangement (9), and a fixed wheel (32) of the countershaft (15) is functionally connected to one of the gearwheels (33) of the countershaft (14) associated with the first shifting element (K1).
19. The transmission device according to claim 15, wherein a further shifting element (K3), arranged on an additional countershaft (16), is provided for obtaining the third driving range.
20. The transmission device according to claim 15, wherein a loose wheel (37) that is connectable in a rotationally fixed manner to the associated countershaft (16) by the third shifting element (K3), by which the third driving range can be obtained when the third shifting element (K3) is in an engaged operating condition, meshes with a further fixed wheel (27; 42) of the first hydrostatic shaft (28) associated with the hydrostatic device (4), and a fixed wheel (38) of the countershaft (16) is functionally connected to the transmission output shaft (18).
21. The transmission device according to claim 15, wherein a fixed wheel (39) of a transmission input shaft (7) can be connected, via a fixed wheel (40) of a further countershaft (13), to a hydraulic pump of a first working hydraulic system, and, via a fixed wheel (41) of an additional countershaft (12), to a hydraulic pump of a second working hydraulic system.
22. The transmission device according to claim 21, wherein the transmission input shaft (7) can be brought into functional connection with a planetary carrier (24) of the planetary gear system (9) by driving direction shifting elements (KR, KV).
23. The transmission device according to claim 22, wherein the fixed wheels (39, 40, 41) are arranged between the driving direction shifting elements (KR, KV) and the transmission input shaft (7).
24. The transmission device according to claim 23, wherein the driving direction shifting elements (KR, KV) are arranged between the fixed wheels (39, 40, 41) and the transmission input shaft (7).
25. A transmission device (1) with power branching, the transmission device comprising:
first and second power branches (3, 5) and a planetary gear system (9) for summing applied torques that are transmitted by the first and the second power branches (3, 5);
a hydrostatic device (4) having first and second hydraulic units (10, 11), the first hydraulic unit (10) coupling a first hydrostatic shaft (29) and the second hydraulic unit (11) coupling a second hydrostatic shaft (28) such that, in each of the first and the second power branches (3, 5), first, second and third driving ranges, in forward and reverse drive, can be implemented and shifted between by disengagement of at least one of a plurality of shifting element (K1, K2, K3) and engagement of at least one of the plurality of shifting element (K1, K2, K3), and each of the plurality of shifting elements (K1, K2, K3) being supported on a respective one of first, second and third counter shaft (14, 15 16);
the planetary gear system (9) comprises first and second sun gears (21, 22) engaging with common double planetary gear wheels (23), a ring gear (25) and a planetary carrier (24), the second sun gear (22) being fixedly coupled to the first hydrostatic shaft (29) and the ring gear (25) being directly connected to a first fixed wheel (26) which engages a second fixed wheel (27) that is fixedly coupled to the second hydrostatic shaft (28);
in the first and the third driving ranges, the applied torques of the first and the second power branches (3, 5) being summed by the second hydrostatic shaft (28) connected to the second hydraulic unit (11);
the second fixed wheel (27) and a third fixed wheels (36) being fixedly coupled to the second hydrostatic shaft (28) such that one half of a first of the plurality of shifting elements (K1) being functionally connected, via a gear wheel (33; 43) of the first counter shaft (14), to a transmission output shaft (8), by which the first driving range is implemented in an engaged operating condition of the first shifting element (K1), and another half of the first shifting element (K1) being functionally connected, via another gear wheel (35) of the first counter shaft (14), to the second hydrostatic shaft (28) connected to the hydrostatic device (4);
one of either an inner or an outer disk carrier of the first shifting element (K1) being connected to the first counter shaft (14) and the other of the outer or the inner disk carrier of the first shifting element (K1) being connected to the gear wheel (35 or 33) which is couplable, via the first shifting element (K1), to the first counter shaft (14) such that the gear wheel (35 or 33) that is couplable, via the first shifting element (K1), to the first counter shaft (14) being functionally connected to the transmission output shaft (8), and the gear wheel (33 or 35 or 43) of the first counter shaft (14) meshing with a fixed wheel (36) of the second hydrostatic shaft (28) that is associated with the hydrostatic device (4).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for testing non-volatile memory devices that have at least one parallel communication interface, and have a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal; wherein a subsequent reading operation is started upon the fall edge of said control signal.
2. A method according to claim 1, wherein a second ATD signal is generated concurrently with the start of said subsequent reading operation.
3. A method according to claim 1, wherein two memory locations are read at each cycle of said control signal.
4. A method according to claim 2, wherein said second ADT signal enables a full reading cycle.
5. A method according to claim 4, wherein the duration of said full reading cycle is less than 100 ns.
6. A method according to claim 1, wherein said subsequent reading occurs after only the columns in the internal addresses are stored.
7. An electronic memory device, being monolithically integrated on a semiconductor and having at least one parallel interface and a matrix of non-volatile memory cells with respective row and column decoding circuits and circuits for reading, changing and erasing the contents of the memory cells, the memory device comprising a first generator block for generating impulsive row and column address signals, said first generator block receiving a control signal, and comprises a second generator block for generating an ATD signal, said second generator block receiving in turn said control signal and being operatively linked to both the rise and the fall edge of said control signal.
8. A device according to claim 7, further comprising an address storage block being input an address bus and impulsive signals from said first generator block in order to temporarily store only the column addresses upon the rise edge of said control signal being received.
9. A device according to claim 7, wherein it is a flash memory.
10. A method, comprising:
accessing a first location of a memory in response to a first transition of a control signal;
generating a first address-transition-detection pulse in response to a second transition of the control signal, the second transition being opposite to the first transition; and
accessing a second location of the memory in response to the address-transition-detection pulse.
11. The method of claim 10 wherein:
the first transition comprises a falling edge of the control signal; and
the second transition comprises a rising edge of the control signal.
12. The method of claim 10 wherein:
the first transition comprises a rising edge of the control signal; and
the second transition comprises a falling edge of the control signal.
13. A method, comprising:
accessing a first location of a memory in response to a first transition of a control signal;
accessing a second location of the memory in response to a second transition of the control signal, the second transition being opposite to the first transition;
wherein accessing the first location comprises,
storing a column address in response to the first transition of the control signal, and
providing to the memory a location address that includes the column address and a first row address stored before the first transition of the control signal; and
wherein accessing the second location comprises,
storing a second row address in response to the second transition of the control signal, and
providing to the memory a location address that includes the column address and the second row address.
14. A method, comprising:
accessing a first location of a memory in response to a first transition of a control signal;
accessing a second location of the memory in response to a second transition of the control signal, the second transition being opposite to the first transition;
wherein accessing the first location comprises,
storing a row address in response to the first transition of the control signal, and
providing to the memory a location address that includes the row address and a first column address stored before the first transition of the control signal; and
wherein accessing the second location comprises,
storing a second column address in response to the second transition of the control signal, and
providing to the memory a location address that includes the row address and the second column address.
15. The method of claim 10 wherein:
accessing the first location comprises writing data to the first location; and
accessing the second location comprises writing data to the second location.
16. The method of claim 10 wherein:
accessing the first location comprises reading data from the first location; and
accessing the second location comprises data from the second location.
17. An integrated circuit, comprising:
a nonvolatile memory having multiple locations;
a control node operable to receive a control signal having first-type edges and opposite second-type edges; and
a memory-access circuit coupled to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal.
18. An integrated circuit, comprising:
a memory having multiple locations;
a control node operable to receive a control signal having first-edged and opposite second-type edges;
a memory-access circuit couple to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal; and
wherein the memory-access circuit comprises an address-transition-detect generator that is operable to,
access the first location of the memory by generating a first address-transition-detect pulse in response to the first-type edge of the control signal, and
access the second location of the memory by generating a second address-transition-detect pulse in response to the second-type edge of the control signal.
19. An integrated circuit, comprising:
a memory having multiple locations;
a control node operable to receive a control signal having first-type edges and opposite second-type edges;
a memory-access circuit coupled to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal;
address nodes; and
wherein the memory access circuit is coupled to the address nodes and comprises an address latch that is operable to,
in response to the first-type edge of the control signal, latch from the address nodes a column address of the first and second locations and provide to the memory the column address and a previously latched row address of the first location, and
in response to the second-type edge of the control signal, latch from the address nodes a row address of the second location and provide to the memory the column address and the row address of the second location.
20. An integrated circuit, comprising:
a memory having multiple locations;
a control node operable to receive a control signal having first-type edges and opposite second-type edges;
a memory-access circuit coupled to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal;
address nodes; and
wherein the memory access circuit is coupled to the address nodes and comprises an address latch that is operable to,
in response to the first-type edge of the control signal, latch from the address nodes a row address of the first and second locations and provide to the memory the row address and a previously latched column address of the first location, and
in response to the second-type edge of the control signal, latch from the address nodes a column address of the second location and provide to the memory the row address and the column address of the second location.
21. An integrated circuit, comprising:
a memory having multiple locations;
a control node operable to receive a control signal having first-type edges and opposite second-type edges;
a memory-access circuit coupled to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal; and
wherein the memory-access circuit is further operable to,
access the first and second locations of the memory in response to the first-type and second-type edges of the control signal during a test mode of operation; and
access the first and second locations of the memory in response to only the first-type edges of the control signal during a normal mode of operation.
22. An electronic system, comprising:
an integrated circuit having,
a nonvolatile memory having multiple locations,
a control node operable to receive a control signal having first-type edges and opposite second-type edges, and
a memory-access circuit coupled to the memory and to the control node and operable to,
access a first location of the memory in response to a first-type edge of the control signal, and
access a second location of the memory in response to a second-type edge of the control signal.
23. A method for testing a memory, comprising:
recognizing a fall in a clock control signal and at that time in the cycle,
reading a column address,
generating a column pulse signal,
generating a first memory address with column decoding information,
generating a first address transition detection signal,
generating a first read control signal,
generating a first sense-amplifier latch signal,
reading a first memory address, and
outputting a first data on a parallel interface, and subsequently recognizing a rise in a clock control signal and at that time in the cycle,
reading a row address,
generating a row pulse signal,
generating a second memory address with row decoding information based on the row address and column decoding information left unchanged,
generating a second address transition detection signal,
generating a second read control signal,
generating a second sense-amplifier latch signal,
reading a second memory address, and
outputting a second data on a parallel interface.
24. The method of claim 10 wherein accessing the first location of the memory comprises:
generating a second address-transition-detection pulse in response to the first transition of the control signal; and
accessing the first location of the memory in response to the second address-transition-detection pulse.
25. A method, comprising:
accessing a first location of a nonvolatile memory in response to a first transition of a control signal; and
accessing a second location of the nonvolatile memory in response to a second transition of the control signal, the second transition being opposite to the first transition.