1. A single-ended memory read circuit configured to operate in a first mode or in a second mode, comprising:
a pre-charge circuit configured to pull up a first bit line and a second bit line in response to a pre-charge control signal;
a bit keeper circuit configured to maintain a high state whenever the first bit line or the second bit line is in a high state, wherein the bit keeper is disabled when the single-ended memory circuit operates in the first mode and the bit keeper circuit is periodically disabled by a timer circuit when the single-ended memory circuit operates in the second mode; and
a column select circuit configured to select either the first bit line or the second bit line to drive an output node located within the column select circuit to produce a single bit of read data.
2. The memory read circuit of claim 1, wherein the pre-charge circuit includes a first p-channel field effect transistor (P-FET) configured to provide a first pull-up path from the first bit line to a voltage supply.
3. The memory read circuit of claim 2, wherein the pre-charge circuit includes a second P-FET configured to provide a second pull-up path from the second bit line to the voltage supply.
4. The memory read circuit of claim 3, wherein the bit keeper circuit includes a third P-FET, a fourth P-FET and a first inverter configured to provide a third pull-up path from the first bit line to the voltage supply.
5. The memory read circuit of claim 4, wherein the bit keeper circuit includes a fifth P-FET, a sixth P-FET and a second inverter configured to provide a fourth pull-up path from the second bit line to the voltage supply.
6. The memory read circuit of claim 5, wherein the third pull-up path is enabled by a low bit keeper control signal when the first bit line is in a high state.
7. The memory read circuit of claim 6, wherein the first bit line is pulled up to the voltage supply when the third pull-up path is enabled.
8. The memory read circuit of claim 5, wherein the fourth pull-up path is enabled by low bit keeper control signal when the second bit line is in a high state.
9. The memory read circuit of claim 8, wherein the second bit line is pulled up to the voltage supply when the fourth pull-up path is enabled.
10. The memory read circuit of claim 5, wherein the column select circuit includes a third inverter and a first gated inverter configured to drive the output node with an inverted representation of a first bit line signal in response to a first column select signal having a high value.
11. The memory read circuit of claim 10, wherein the column select circuit includes a fourth inverter and a second gated inverter configured to drive the output node with an inverted representation of a second bit line signal in response to a second column select signal having a high value.
12. The memory read circuit of claim 11, further comprising an output latch circuit configured to latch a value associated with the output node.
13. The memory read circuit of claim 12, wherein the output latch circuit is further configured to generate an inverted representation of the latched value.
14. The memory read circuit of claim 13, wherein the output latch circuit includes a first n-channel field effect transistor (N-FET), a second N-FET, a third N-FET and a fifth inverter configured to pull down the output node to a low state in response to the first column select signal and the second column select signal being in low states.
15. The memory read circuit of claim 14, wherein the output latch circuit includes a seventh P-FET, an eighth P-FET and a ninth P-FET configured to pull up the output node, in combination with the fifth inverter, to the voltage supply in response to the first column select signal and the second column select signal being in low states.
16. The memory read circuit of claim 1, wherein the bit keeper circuit is driven by a bit keeper control signal produced by a pulse generator circuit.
17. The memory read circuit of claim 1, wherein the memory read circuit operates at a higher frequency in the first mode than in the second mode.
18. The memory read circuit of claim 1, wherein the bit keeper circuit is enabled prior to a read operation or a write operation when the memory read circuit operates in the second mode.
19. An integrated circuit, comprising:
logic circuits; and
a memory circuit coupled to the logic circuits and including a single-ended memory read circuit configured to operate in a first mode or in a second mode, having:
a pre-charge circuit configured to pull up a first bit line and a second bit line in response to a pre-charge control signal,
a bit keeper circuit configured to maintain a high state whenever the first bit line or the second bit line is in a high state, wherein the bit keeper is disabled when the single-ended memory circuit operates in the first mode and the bit keeper circuit is periodically disabled by a timer circuit when the single-ended memory circuit operates in the second mode, and
a column select circuit configured to select either the first bit line or the second bit line to drive an output node located within the column select circuit to produce a single bit of read data.
20. The integrated circuit of claim 19, wherein the bit keeper circuit includes a third P-FET, a fourth P-FET and a first inverter configured to provide a third pull-up path from the first bit line to the voltage supply, and a fifth P-FET, a sixth P-FET and a second inverter configured to provide a fourth pull-up path from the second bit line to the voltage supply.
21. The integrated circuit of claim 20, wherein the third pull-up path is enabled by a low bit keeper control signal when the first bit line is in a high state, and the fourth pull-up path is enabled by a low bit keeper control signal when the second bit line is in a high state.
22. The integrated circuit of claim 21, wherein the first bit line is pulled up to the voltage supply when the third pull-up path is enabled, and the second bit line is pulled up to the voltage supply when the fourth pull-up path is enabled.
23. The integrated circuit of claim 19, wherein the memory read circuit operates at a higher frequency in the first mode than in the second mode.
24. The integrated circuit of claim 19, wherein the bit keeper circuit is enabled prior to a read operation or a write operation when the memory read circuit operates in the second mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A gyroscope based radio transmitter system for a radio controlled (RC) vehicle such as a car or a boat, which allows the user to direct the vehicle by using a more ergonomic steering wheel and a pedal. Said system can be carried easily to indoor or outdoor tracks by folding the steering wheel base and also can be used for different RC vehicles by different users. The system comprising:
A gyroscope based steering wheel
Said parts are:
Bearing to rotate the steering wheel, Antenna, Gyroscope module, Microprocessor, 2.4 GHz transreceiver, Battery
A pedal for acceleration and braking
Said parts are:
Base, Leveler, Springs, Magnet, Hall effect sensor, Antenna, Gyroscope module, Microprocessor, 2.4 GHz transreceiver, Battery
A screen display to communicate with the user
Said parts are:
LCD screen, Control buttons, Antenna, Gyroscope module, Microprocessor, 2.4 GHz transreceiver, Battery
A foldable base for the steering wheel assembly
Said parts are:
Bearing base for the steering wheel, Carrying hole, Antenna, Gyroscope module, Microprocessor, 2.4 GHz transreceiver, Battery
A transreceiver to be located on the RC vehicle
Said parts are:
Antenna, Gyroscope module, Microprocessor, 2.4 GHz transreceiver
Said RC vehicle with an engine and wheels for cars or steering mechanism for boats.
2. A gyroscope based radio transmitter system of claim 1, further comprising a user administrative system consists of an LCD screen display and user control buttons or means that allows users:
to assign certain user settings to certain users
to assign certain RC vehicles to certain users
to monitor key telemetries from the RC vehicle
3. A gyroscope based radio transmitter system of claim 1, further comprising a method for the user
to couple the physical orientations of the RC vehicle and the radio transmitter by using gyroscopes located on both system components
to alert the user with visual signs and sound then perform the stability control tasks automatically when the certain rotational forces of the RC vehicle are reached to the thresholds set by the user
to provide user a radio control design similar to real life vehicle driving experience. Radio transmitter consists of a round shaped steering wheel knob that is close to the size of a palm of a human being. The same system has a pedal to be used by the foot to simulate the real life vehicle driving experience.
to collect and analyze the usage history data by user to keep record of the usage date, time and RC vehicle telemetry data such as speed, RPM, battery level and temperature.