1. A method of fault-tolerant clocking comprising the steps of:
generating, by a first process controller, a first digital data value;
receiving the first digital data value, a first input reference signal and a first clock signal in a master clock synthesizer circuit;
generating a first output clock signal of a predetermined frequency by the master clock synthesizer circuit by converting the first digital data value to the first output clock signal at a conversion rate determined by the first clock signal;
receiving the first output clock signal of the master clock synthesizer circuit and a second clock signal in a slave clock synthesizer circuit;
generating a second output clock signal by the slave clock synthesizer circuit in response to the first output clock signal of the master clock synthesizer circuit and the second clock signal; and
transmitting the second output clock signal of the slave clock synthesizer circuit to the master clock synthesizer circuit as the first input reference signal.
2. The method of claim 1, further comprising the step of verifying validity of the first output clock signal of the master clock synthesizer circuit.
3. The method of claim 2, further comprising the step of performing a function of the master clock synthesizer circuit by the slave clock synthesizer circuit, if the first output clock signal is deemed invalid.
4. The method of claim 1, further comprising the step of performing a function of the master clock synthesizer circuit by the slave clock synthesizer circuit, if the master clock synthesizer circuit fails.
5. The method of claim 1, further comprising the step of tracking the first output clock signal of the master clock synthesizer circuit by a second slave clock circuit.
6. The method of claim 1, wherein the step of generating a first output clock signal of a predetermined frequency by the master clock synthesizer circuit is further in response to the first input reference signal.
7. The method of claim 1, further comprising the step of generating, by a second process controller, a second digital data value.
8. The method of claim 7, wherein the first process controller is a first baseboard management controller and the second process controller is a second baseboard management controller.
9. The method of claim 1, further comprising the step of receiving a second digital data stream in the slave clock synthesizer circuit.
10. The method of claim 9, wherein the step of generating a second output clock signal by the slave clock synthesizer circuit is further in response to the second digital data stream.
11. The method of claim 1, wherein the frequency of the first output clock signal varies within a predetermined range of frequencies.
12. The method of claim 1, further comprising the steps of generating, by a first crystal oscillator, the first clock signal and generating, by a second crystal oscillator, the second clock signal.
13. A fault-tolerant clocking apparatus comprising:
a first clock synthesizer circuit configured to receive a first input reference signal, a first digital data value and a first clock signal and, in response to the first clock signal, the first clock synthesizer circuit determining a rate of conversion of the first digital data value into a first output clock signal of a predetermined frequency, and
a second clock synthesizer circuit in data communication with the first clock synthesizer circuit configured to receive the first output clock signal of the first clock synthesizer circuit and a second clock signal and generate a second output clock signal in response to the first output clock signal and the second clock signal, wherein the first clock synthesizer circuit is further configured to receive the second output clock signal as the first input reference signal.
14. The apparatus of claim 13, wherein the second clock synthesizer circuit is further configured to verify validity of the first output clock signal of the first clock synthesizer circuit.
15. The apparatus of claim 14, wherein the second clock synthesizer circuit is further configured to perform a function of the first clock synthesizer circuit, if the first output clock signal is deemed invalid.
16. The apparatus of claim 13, wherein the second clock synthesizer circuit is further configured to perform a function of the first clock synthesizer circuit, if the first clock synthesizer circuit fails.
17. The apparatus of claim 13, further comprising a first process controller configured to generate the first digital data value and a second process controller configured to generate a second digital data value.
18. The apparatus of claim 17, wherein the second clock synthesizer circuit is further configured to receive the second digital data value.
19. The apparatus of claim 18, wherein the second clock synthesizer circuit is further configured to generate the second output clock signal in response to the second digital data value.
20. The apparatus of claim 13, wherein the first clock synthesizer circuit is further configured to generate the first output clock signal of a predetermined frequency in response to the first input reference signal.
21. The apparatus of claim 13, wherein the frequency of the first output clock signal varies within a predetermined range of frequencies.
22. The apparatus of claim 13, further comprising a first crystal oscillator configured to generate the first clock signal and a second crystal oscillator configured to generate the second clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a TFTEC structure comprising;
forming at least one buried electrode within a substrate, wherein the at least one buried electrode comprises one of a p doped and an n doped silicon region of the substrate;
forming a first plurality of openings through a first surface of the substrate,
forming a p-type TFTEC material within the first plurality of openings;
forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate; and
forming an n-type TFTEC material within the second plurality of openings.
2. The method of claim 1 wherein at least one of the first plurality and second plurality of openings comprises a depth of about 50 microns to about 200 microns.
3. The method of claim 1 wherein at least one of the first plurality and second plurality of openings is formed by reactive ion etching.
4. The method of claim 1 wherein forming at least one of the p-type TFTEC material and the n-type TFTEC material comprises forming at least one of bismuth, tellurium, selenium, germanium, antimony and silicon, and combinations thereof.
5. The method of claim 1 wherein forming the p-type TFTEC material within the first plurality of openings and forming the n-type TFTEC material within the second plurality of openings comprises forming a plurality of p-type TFTEC legs and a plurality of n-type TFTEC legs.
6. The method of claim 5 further comprising forming conductive traces on a top surface of at least one of the plurality of p-type TFTEC legs and a top surface of at least one of the plurality of n-type TFTEC legs.
7. The method of claim 5 wherein the at least one buried electrode is disposed on a bottom surface of at least one of the plurality of p-type TFTEC legs and a bottom surface of at least one of the plurality of n-type TFTEC legs.
8. The method of claim 5 further comprising wherein at least one of the plurality of p-type TFTEC legs and at least one of the plurality of n-type TFTEC legs are electrically coupled together to form a heat pumping structure.