What is claimed is:
1. A semiconductor memory device, comprising:
a plurality of memory blocks each having a plurality of normal memory cells;
a plurality of spare memory blocks provided corresponding to said plurality of memory blocks each for repairing a defective normal memory cell in a corresponding memory block;
a plurality of local data buses provided corresponding to said plurality of memory blocks each for transferring data with a corresponding memory block;
a plurality of spare local data buses provided corresponding to said plurality of spare memory blocks each for transferring data with a corresponding spare memory block;
a global data bus provided in common to said plurality of memory blocks and selectively coupled with a local data bus provided corresponding to a memory block including a selected normal memory cell; and
a spare global data bus provided in common to said plurality of spare memory blocks and coupled simultaneously and selectively with a spare local data bus provided corresponding to k spare memory blocks including a spare memory block including a selected spare memory cell, said k being an integer no less than two.
2. The semiconductor memory device as recited in claim 1, wherein
a value of said k is given by the capacitance ratio of one spare local data bus and one local data bus.
3. The semiconductor memory device as recited in claim 1, wherein
said plurality of normal memory cells are arranged in a matrix of rows and columns in each of the memory blocks, each of the memory blocks is divided into a plurality of memory sub-arrays along a row direction, and
spare memory cells in each of the spare memory blocks are arranged in a matrix of rows and columns, and each column of spare memory cells can replace a column including a defective memory cell in any of the memory sub-arrays in a corresponding memory block.
4. A semiconductor memory device, comprising:
a plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns; and
a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks,
each row of said plurality of spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of first memory blocks.
5. The semiconductor memory device as recited in claim 4, further comprising:
a plurality of second memory blocks arranged alternately with said plurality of first memory blocks along a column direction, the second memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns; and
a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of second memory blocks, each row of said spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of second memory blocks.
6. The semiconductor memory device as recited in claim 5, further comprising a plurality of sense amplifier bands one provided between each of said plurality of first memory blocks and each of said plurality of second memory blocks, and shared by adjacent memory blocks in the column direction for sensing and amplifying data in each column of a memory block including a selected memory cell when activated.
7. The semiconductor memory device as recited in claim 6, wherein
said plurality of first memory blocks, said plurality of second memory blocks and said plurality of sense amplifier bands form a first memory array, and wherein
said semiconductor memory device further comprises:
a second memory array having a same arrangement as the first memory array; and
control circuitry for driving one memory block from the first and second memory arrays into a selected state in a normal operation mode, and for simultaneously driving a prescribed number of memory blocks from each of said first and second memory arrays into a selected state in a particular operation mode.
8. A semiconductor memory device, comprising:
a plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns;
a plurality of second memory blocks provided alternately with said plurality of first memory blocks along a column direction, of the memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns;
a plurality of third memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns;
a plurality of fourth memory blocks provided alternately with said third memory blocks in the column direction of the fourth memory blocks having a plurality of normal memory cells;
a first spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in the third memory blocks;
a second spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said second memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of fourth memory blocks;
a third spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said third memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of first memory blocks;
a fourth spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of fourth memory block, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of second memory blocks; and
control circuitry for selectively driving one of the first to fourth memory blocks into a selected state in a normal operation mode, and selecting one of first and second memory blocks and one of the third and fourth memory blocks to drive selected memory blocks into a selected state in a particular operation mode.
9. The semiconductor memory device as recited in claim 8, further comprising a plurality of sense amplifier bands provided one between each of said plurality of first memory blocks and each of said plurality of second memory blocks and one between each of said plurality of third memory blocks and each of said plurality of fourth memory blocks, shared between adjacent memory blocks in the column direction, and activated when a corresponding memory block is driven into a selected state, for sensing and amplifying data in each column of the corresponding memory block.
10. The semiconductor memory device as recited in claim 8, wherein
said control circuitry selects and drives a memory block of said plurality of third memory blocks when a memory block of said plurality of first memory blocks is selected in said particular operation mode.
11. A semiconductor memory device capable of operating in a normal mode for accessing data and in a refresh mode for holding data, comprising:
a power source node for supplying a prescribed voltage;
a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns and a repeating circuit group including a plurality of repeating circuits each having a common function for performing an operation related to a memory cell selection;
a plurality of power source switch circuits provided corresponding to said plurality of memory blocks, each of the power source switch circuits for coupling said power source node and a repeating circuit group in a corresponding memory block, said plurality of power source switch circuits each causing a first current flow in a selected state and a second current flow smaller than said first current in a non-selected state; and
control circuitry for selectively driving said plurality of power source switch circuits into a selected state according to an address signal such that the number of selected power source switch circuit(s) is different between said normal mode and said refresh mode.
12. The semiconductor memory device as recited in claim 11, wherein
said control circuitry includes a circuit for generating a control signal for selecting a power source switch circuit by decoding a first number of address bits in said normal mode and generating said control signal by decoding a second number of address bits in said refresh mode, said second number being greater than said first number.
13. The semiconductor memory device as recited in claim 11, wherein
said plurality of memory blocks are divided into a plurality of global blocks each having a plurality of memory blocks, and
said control circuitry includes a circuit for decoding an address bit specifying a global block of said plurality of global blocks in said normal mode, and for decoding an address bit specifying a memory block of said plurality of memory blocks in said refresh mode.
14. The semiconductor memory device as recited in claim 11, wherein
said plurality of memory blocks each include a plurality of word lines provided corresponding to each row of memory cells, and wherein
said semiconductor memory device further comprises,
delay circuitry for delaying a timing of driving a word line provided corresponding to an addressed row into a selected state in said refresh mode behind the timing in said normal mode.
15. The semiconductor memory device as recited in claim 11, wherein
said plurality of memory blocks each include a plurality of word lines provided corresponding to memory cell rows, and
said control circuitry includes a circuit for generating said control signal in said refresh mode such that a power source switch circuit provided for a memory block including an addressed word line is selected and power source switch circuits provided corresponding to remaining memory blocks are set in a non-selected state.
16. The semiconductor memory device as recited in claim 11, further comprising count circuitry responsive to activation of a count instruction signal for performing a counting operation to generate a refresh address in said refresh mode, wherein
said control circuitry includes,
a first decode circuit for decoding a prescribed bit of said refresh address to generate and latch a next control signal, and
a circuit for applying the next control signal latched by said first decode circuit in response to a refresh cycle instruction signal applied after completion of the decoding operation by said first decode circuit in said refresh mode,
said count instruction signal is activated in an activation period of said refresh cycle instruction signal and said refresh address specifies a refresh row to be refreshed in a refresh cycle started by said refresh cycle instruction signal.
17. The semiconductor memory device as recited in claim 11, wherein
a particular memory block of said plurality of memory blocks includes a spare element for repairing a defective cell by replacement, said spare element being capable of repairing a defective cell in any of said plurality of memory blocks, and
said control circuitry includes a circuit for selecting a power source switch circuit for said particular block regardless of said address signal in said normal mode and for selectively driving a power source switch circuit provided corresponding to said particular memory block according to the result of determination of whether said address signal addresses a memory cell to be repaired in the refresh mode.
18. The semiconductor memory device as recited in claim 17, further comprising counting circuitry responsive to a count instruction signal for performing a counting operation to generate a refresh address in said refresh mode, wherein
said control circuitry includes,
a first decode circuit for decoding a prescribed bit of said refresh address to generate and latch a next control signal, and
a circuit responsive to activation of a refresh cycle instruction signal applied after completion of the decoding operation by said first decode circuit for applying the control signal latched by said first decode circuit to said plurality of power source switch circuits in said refresh mode, said count instruction signal is activated in an activation period of said refresh cycle instruction signal, said refresh address specifying a refresh row in a refresh cycle started by said refresh cycle instruction signal.
19. The semiconductor memory devise as recited in claim 11, wherein
a particular memory block of said plurality of memory blocks includes a spare element for repairing a defective cell by replacement, said spare element being capable of repairing a defective cell in any of said plurality of memory blocks in said normal mode, and
said control circuitry includes a circuit for driving a power source switch circuit provided corresponding to said particular memory block and an addressed memory block among said plurality of power source switch circuits into a selected state in said normal mode.
20. The semiconductor memory device as recited in claim 17, wherein
said control circuitry includes a circuit for driving a power source switch circuit provided corresponding to said particular memory block and a memory block specified by said address signal into a selected state, and then driving into a non-selected state a power source switch circuit provided corresponding to a memory block excluding a memory block including a memory cell to be driven into a selected state according to the result of said determination and said address signal in said normal mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A training apparatus comprising:
a storing means for storing therein targeted goal command information indicating correct input order of commands necessary to perform a targeted operation for each of individual targeted operations;
recording means for recording inputted data on a recording medium; and
a control means,
wherein the control means conducts
a targeted operation selecting process of selecting one targeted operation from the individual targeted operations based on a user manipulation;
a user input command information generation process of generating user input command information by accumulating a command inputted based on a user manipulation; and
a notification control process of conducting control so as to notify a compared result of the targeted goal command information about a targeted operation selected in the targeted operation selecting process with user input command information generated in the user input command information generation process,
wherein at least one targeted operation in the targeted operations is an operation related to editing data recorded on the recording medium.
2. The training apparatus according to claim 1, wherein the control means conducts a manipulation training process including the targeted operation selecting process, the user input command information generation process, and the notification control process in response to making a predetermined manipulation to instruct switching to a manipulation training mode.
3. A training apparatus comprising:
a storing means for storing therein targeted goal command information indicating correct input order of commands necessary to perform a targeted operation for each of individual targeted operations;
a recording means for recording inputted data on a necessary recording medium; and
a control means,
wherein the control means conducts
a targeted operation selecting process of selecting one targeted operation from the individual targeted operations based on a user manipulation;
a user input command information generation process of generating user input command information by accumulating a command inputted based on a user manipulation;
a notification control process of conducting control so as to notify a compared result of the targeted goal command information about a targeted operation selected in the targeted operation selecting process with user input command information generated in the user input command information generation process,
a manipulation training process including the targeted operation selecting process, the user input command information generation process, and the notification control process in response to making a predetermined manipulation to instruct switching to a manipulation training mode,
wherein at least one targeted operation in the targeted operations is an operation related to recording inputted data by recording means, and
wherein at least one targeted operation in the targeted operations is an operation related to editing data recorded on the recording medium.
4. The training apparatus according to claim 3, further comprising a reproducing means for reproducing data recorded on the recording medium,
wherein at least one targeted operation in the targeted operations is an operation related to reproducing data recorded on the recording medium.
5. The training apparatus according to claim 4, wherein the control means further conducts a management information generation process of generating data management information for managing data such that data to be recorded on the recording medium in response to inputting a command after switching to the training mode is separated from other data recorded on the recording medium.
6. A training method of a training apparatus stored with targeted goal command information indicating correct input order of commands necessary to perform a targeted operation for each of individual targeted operations, the method comprising the steps of:
recording inputted data on a recording medium;
selecting one targeted operation from the individual targeted operations based on a user manipulation;
generating user input command information by accumulating a command inputted based on a user manipulation; and
controlling notification so as to notify a compared result of user input command information generated in the step of generating user input command information with targeted goal command information about a targeted operation selected in the step of selecting a targeted operation,
wherein at least one targeted operation in the targeted operations is an operation related to editing data recorded on the recording medium.
7. A training apparatus comprising:
a storing unit configured to store therein targeted goal command information indicating correct input order of commands necessary to perform a targeted operation for each of individual targeted operations;
a recording unit configured to record inputted data on a recording medium; and
a control unit,
wherein the control unit conducts
a targeted operation selecting process of selecting one targeted operation from the individual targeted operations based on a user manipulation;
a user input command information generation process of generating user input command information by accumulating a command inputted based on a user manipulation; and
a notification control process of conducting control so as to notify a compared result of the targeted goal command information about a targeted operation selected in the targeted operation selecting process with user input command information generated in the user input command information generation process,
wherein at least one targeted operation in the targeted operations is an operation related to editing data recorded on the recording medium.