1. A pixel array substrate structure comprising:
a circuit unit having a plurality of transistor circuits;
an insulating film on a substrate on which the circuit unit is disposed;
a sourcedrain electrode on the insulating film, the sourcedrain electrode being connected to a sourcedrain of each of the transistor circuits;
a first planarizing film, a relay wire, and a second planarizing film, which are sequentially stacked on the insulating film and the sourcedrain electrode;
a first contact portion that is formed in the first planarizing film and connected to the sourcedrain electrode; and
a second contact portion formed in the second planarizing film,
wherein the relay wire electrically connects the first contact portion to the second contact portion that is formed at a position different from the first contact portion when seen from above.
2. The pixel array substrate structure according to claim 1,
wherein the position at which the second contact portion is disposed is appropriately set with respect to the position at which the first contact portion is disposed.
3. The pixel array substrate structure according to claim 1,
wherein the circuit unit includes a memory that holds data in each pixel.
4. The pixel array substrate structure according to claim 1,
wherein the second contact portion is electrically connected to a pixel electrode formed in the second planarizing film and
the pixel electrode is a reflective electrode.
5. The pixel array substrate structure according to claim 4,
wherein the circuit unit includes a driving circuit that drives the pixel electrode through the first contact portion, the relay wire, and the second contact portion.
6. The pixel array substrate structure according to claim 4,
wherein the pixel electrode is divided into a plurality of electrodes.
7. The pixel array substrate structure according to claim 6,
wherein the plurality of electrodes display gradation by using combinations of electrode areas.
8. The pixel array substrate structure according to claim 1,
wherein a contact hole of the second contact portion is formed in a rectangular shape.
9. The pixel array substrate structure according to claim 1,
wherein a region with an inclination angle of 3\xb0 or more is within 1 \u03bcm from the bottom end of the contact hole, in the contact hole of the second contact portion.
10. The pixel array substrate structure according to claim 1,
wherein a glass transition point of the material of the second planarizing film is higher than a firing temperature of the second planarizing film after the second planarizing film is developed.
11. The pixel array substrate structure according to claim 10,
wherein the material of the second planarizing film has a glass transition point that is higher than that of the material of the first planarizing film.
12. The pixel array substrate structure according to claim 1, wherein the relay wire comprises at least two wires connecting between the first contact portion and the second contact portion.
13. A method of manufacturing a pixel array substrate structure, which includes:
a circuit unit having a plurality of transistor circuits;
an insulating film on a substrate on which the circuit unit is disposed;
a sourcedrain electrode on the insulating film, the sourcedrain electrode being connected to a sourcedrain of each of the transistor circuits;
a first planarizing film and a second planarizing film, which are sequentially stacked on the insulating film and the sourcedrain electrode;
a first contact portion that is formed in the first planarizing film and connected to the sourcedrain electrode;
a second contact portion formed in the second planarizing film; and
a relay wire formed between the first and second planarizing films,
in which the relay wire electrically connects the first contact portion to the second contact portion that is formed at a position different from that of the first contact portion when seen from above, the method comprising:
setting a glass transition point of the material of the second planarizing film higher than a firing temperature of the second planarizing film after the second planarizing film is developed.
14. The method of manufacturing a pixel array substrate structure according to claim 13,
wherein a material having a glass transition point higher than that of the first planarizing film is used for the material of the second planarizing film.
15. A display device having a pixel array substrate structure that includes:
a circuit unit having a plurality of transistor circuits;
an insulating film on a substrate on which the circuit unit is disposed;
a sourcedrain electrode on the insulating film, the sourcedrain electrode being connected to a sourcedrain of each of the transistor circuits;
a first planarizing film, a relay wire, and a second planarizing film, which are sequentially stacked on the insulating film and the sourcedrain electrode;
a first contact portion that is formed in the first planarizing film and connected to the sourcedrain electrode; and
a second contact portion formed in the second planarizing film,
wherein the relay wire electrically connects the first contact portion to the second contact portion that is formed at a position different from the first contact portion when seen from above.
16. An electronic apparatus including a display device having a pixel array substrate structure that includes:
a circuit unit having a plurality of transistor circuits;
an insulating film on a substrate on which the circuit unit is disposed;
a sourcedrain electrode on the insulating film, the sourcedrain electrode being connected to a sourcedrain of each of the transistor circuits;
a first planarizing film, a relay wire, and a second planarizing film, which are sequentially stacked on the insulating film and the sourcedrain electrode;
a first contact portion that is formed in the first planarizing film and connected to the sourcedrain electrode; and
a second contact portion formed in the second planarizing film,
wherein the relay wire electrically connects the first contact portion to the second contact portion that is formed at a position different from the first contact portion when seen from above.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
forming a dielectric layer on a substrate containing at least one aluminum oxide layer and at least one zirconium nitride layer using an atomic layer deposition; and
forming an electrically conductive layer on the dielectric layer.
2. The method of claim 1, wherein forming the dielectric layer includes forming an amorphous dielectric.
3. The method of claim 1, wherein the substrate includes at least one conductive layer disposed below the dielectric layer.
4. The method of claim 1, wherein the substrate includes at least two diffused regions having a first conductivity type, separated by a region of a second conductivity type disposed below the dielectric layer and metal layer.
5. The method of claim 1, wherein a ratio of zirconium to aluminum is about 1.
6. The method of claim 1, wherein a dielectric constant of the dielectric layer is about 18.
7. The method of claim 1, wherein the aluminum oxide layer comprises a plurality of individually deposited aluminum oxide layers, and each individual one of the layers is less than or equal to two monolayers in thickness.
8. The method of claim 7, wherein each individual one of the aluminum oxide layers has a thickness of about 1.3 to 1.5 Angstroms.
9. The method of claim 1, wherein the dielectric layer has a root mean square surface roughness that is less than one tenth of the layer thickness.
10. The method of claim 1, wherein the dielectric film is separated from the substrate by a diffusion barrier.
11. A method comprising:
forming a dielectric layer on a substrate comprising a zirconium aluminum oxynitride layer using an atomic layer deposition; and
forming an electrically conductive layer on the dielectric layer.
12. The method of claim 11, wherein the forming comprises:
exposing the substrate surface to a precursor material;
exposing the substrate surface to a first purge material;
exposing the substrate surface to a reactant material to form a first dielectric material having a first intermediate thickness;
exposing the substrate surface to a second purge material to complete a first deposition cycle; and
repeating the first deposition cycle until a final dielectric material thickness is obtained.
13. The method of claim 12, wherein the precursor material comprises a mixture of zirconium tertiary-butoxide and tri-methyl-aluminum.
14. The method of claim 12, wherein the atomic layer deposition is conducted within a vacuum chamber maintained at a temperature of about 300\xb0 C.
15. The method of claim 12, wherein the exposing the substrate surface to a precursor material includes a first time period between 0.3 and 2 seconds.
16. The method of claim 12, wherein the exposing the substrate surface to a precursor material includes using a flow volume of the first precursor material sufficient to saturate the substrate surface with the first precursor material.
17. The method of claim 12, wherein the exposing the substrate surface to a precursor material includes using a first flow volume of zirconium tertiary-butoxide, and a second flow volume of trimethyl-aluminum.
18. The method of claim 17, wherein the zirconium tertiary-butoxide has an approximate formula of (Zr(t-OC4H9)4), and the trimethyl-aluminum has an approximate formula of Al(CH3)3.
19. The method of claim 12, wherein the exposing the substrate surface to a first purge material includes using a flow time period sufficient to remove substantially all of a non-adsorbed portion of the first precursor material from the substrate surface.
20. The method of claim 12, wherein the exposing the substrate surface to a reactant material includes using at least one reactant material selected from water vapor, oxygen, ozone, hydrogen peroxide, ammonia and nitrous oxide, and includes using a flow time period sufficient to react with the adsorbed portion of the first precursor material on the substrate surface.
21. A method of forming a gate dielectric, comprising:
exposing a substrate surface at a temperature between 250\xb0 C. to 350\xb0 C. to a precursor material including zirconium tertiary-butoxide and trimethyl-aluminum for a time period of between 0.3 to 2.0 seconds;
exposing the substrate surface to at least one first purge material selected from hydrogen, helium, neon, nitrogen, and argon for a time period of between 1 to 5 seconds;
exposing the substrate surface to at least one reactant material including water vapor, oxygen, hydrogen peroxide, ozone and nitrous oxide for a time period of between 0.5 to 5.0 seconds to form a first dielectric material having a thickness ranging from 0.1 to 0.2 nanometers and a formula of approximately ZrAlON;
exposing the substrate surface to at least one second purge material selected from hydrogen, helium, neon, nitrogen, and argon for a time period of between 1 to 5 seconds to complete a first deposition cycle; and
repeating the first deposition cycle until a final dielectric material thickness is obtained.
22. The method of claim 21, wherein the ZrAlON layer comprises a substantially continuous layer having a root mean square surface roughness of less than 0.5 nanometers and a current leakage rate of less than 1.1\xd710\u22127 amps per cm2 at an electric field strength of 1 megavolt per cm.
23. The method of claim 21, further including:
forming metallization lines in a metal layer disposed above and in contact with the ZrAlON layer to form a gate electrode in an integrated circuit; and
annealing the device in a H2 ambient after forming the metallization lines.
24. The method of claim 21, wherein the first dielectric material has a formula of ZrXAl2-XOYN2-Y, where X and Y are each from 0.5 to 1.5.
25. A method comprising:
coupling an integrated circuit to a controller, wherein the integrated circuit includes a dielectric layer contacting a conductive layer, the dielectric layer comprising ZrXAl2-XOYN2-Y, where X and Y are each between 0.5 to 1.5, wherein forming the dielectric layer contacting the conductive layer includes:
forming the dielectric layer by atomic layer deposition including at least one precursor selected from zirconium tertiary-butoxide, zirconium tetrachloride, zirconium tetraiodide, tetrakis-diethylamino zirconium, homoleptic(tetrakisdialkyloamido) zirconium, trimethyl-aluminum, and dimethylethyl-amino aluminum; and
forming the dielectric layer including at least one reactant selected from water vapor, oxygen, hydrogen peroxide, ozone, ammonia and nitrous oxide.
26. The method of claim 25, wherein the dielectric layer is formed of an interleaved series of aluminum oxide layers and zirconium nitride layers.
27. The method of claim 25, wherein the dielectric layer is formed in a vacuum chamber at a temperature of about 300\xb0 C.
28. An electronic device comprising:
an amorphous dielectric layer containing an atomic layer deposited dielectric layer of zirconium nitride and an atomic layer deposited dielectric layer of aluminum oxide in an integrated circuit; and
a conductive layer contacting the dielectric layer.
29. The electronic device of claim 28, wherein the electronic device includes a transistor in the integrated circuit, the transistor having the dielectric layer as a gate insulator and the conductive layer as a gate in the transistor.
30. The electronic device of claim 28, wherein the zirconium nitride and aluminum oxide layers are thermally treated to form a single layer of ZrXAl2-XOYN2-Y, where X and Y are each between 0.5 to 1.5.
31. The electronic device of claim 30, wherein X=1 and Y=1.
32. The electronic device of claim 30, wherein the dielectric layer has a dielectric constant of about 18.
33. The electronic device of claim 28, wherein the electronic device includes a capacitor having the dielectric layer as a dielectric material between two electrodes in the capacitor, and the conductive layer as at least one of the two electrodes.
34. The electronic device of claim 28, further comprising:
a controller coupled to the electronic device, wherein the electronic device includes:
a dielectric layer comprising atomic layer deposited dielectric layers of zirconium nitride and aluminum oxide in an integrated circuit; and
a conductive layer contacting the dielectric layer.
35. The electronic device of claim 28, wherein the electronic device includes at least one of memory, a logic device, a mixed signal device, a capacitor, a bipolar transistor, a MOS transistor, a telecommunication device, a display, a set top box, or a portion of a vehicle.
36. An electronic device comprising:
an amorphous dielectric layer containing an atomic layer deposited dielectric layer of zirconium aluminum oxynitride disposed over a semiconductor substrate; and
a conductive material contacting the dielectric layer.
37. The electronic device of claim 28, wherein the zirconium aluminum oxynitride layer has a dielectric constant of 17 to 19, and a formula of ZrXAl2-XOYN2-Y, where X and Y are each between 0.75 to 1.25.