What is claimed is:
1. A process for protecting a gas purification system from damage comprising:
a) passing a first impurity-containing gas stream into a data analyzer flow scheme;
b) passing a second reactant-containing gas stream into the analyzer flow scheme;
c) mixing said first impurity-containing gas stream with the second reactant-containing gas stream to form a mixed gas stream;
d) passing said mixed gas stream to a first temperature measuring device to determine its temperature and passing the resulting temperature data to a data analyzer;
e) passing the mixed gas stream from step d) to a catalytic bed to allow the reaction in the mixed gas stream to proceed, and forming a reacted mixed gas stream;
f) passing the reacted mixed stream to a second temperature measuring device to determine its temperature and passing the resulting temperature data to said data analyzer; and
g) controlling the flow of the first impurity-containing gas stream passing to or from the gas purification apparatus based on data received from the data analyzer.
2. The process of claim 1 further comprising passing said first impure gas stream through a flow control device.
3. The process of claim 1 further comprising passing said second reactant-containing gas stream through a flow control device.
4. The process of claim 1 further comprising passing said first impure gas stream through a pressure gauge.
5. The process of claim 1 further comprising passing said second reactant containing gas stream through a pressure gauge.
6. The process of claim 1 wherein said temperature measuring device is a thermocouple.
7. The process of claim 1 wherein said reaction vessel comprises a catalyst bed.
8. The process of claim 1 wherein said catalyst bed is comprised of palladium on a substrate.
9. The process of claim 1 which comprises passing said mixed gas stream to a plurality of temperature measuring devices and catalytic beds in parallel to determine the temperature of the reaction in the catalytic beds.
10. A process for protecting a gas purification system from damage comprising:
a) passing a first impurity-containing gas stream into a data analyzer flow scheme and a gas purification apparatus;
b) passing a second reactant-containing gas stream into the analyzer flow scheme;
c) mixing said first impurity-containing gas stream with the second reactant-containing gas stream to form a mixed gas stream;
d) separating the mixed gas stream into a plurality of split streams;
e) passing one of the split streams to a first temperature measuring device to determine its temperature and passing the resulting temperature to a data analyzer;
f) passing the resulting split stream from step e) to a reaction vessel to purify said resulting split stream;
g) passing the resulting split stream from step f) to a second temperature measuring device to determine its temperature and passing the resulting temperature to the data analyzer;
h) repeating the steps of e) to g) with another split stream through corresponding temperature measuring devices and reaction vessels; and
i) controlling the flow of the first impurity-containing gas stream passing to the gas purification apparatus based on data received from the data analyzer.
11. The process of claim 10 further comprising passing said first impurity-containing gas stream through a flow control device.
12. The process of claim 10 further comprising passing said second reactant-containing gas stream through a flow control device.
13. The process of claim 10 further comprising passing said first impurity-containing gas stream through a pressure gauge.
14. The process of claim 10 further comprising passing said second reactant-containing gas stream through a pressure gauge.
15. The process of claim 10 wherein said temperature measuring device is a thermocouple.
16. The process of claim 10 wherein said reaction vessel comprises a catalyst bed.
17. A system for protecting a gas-purification system from damage comprising:
a) a first impure gas stream;
b) a second reactant containing gas stream;
c) a reactor vessel;
d) a plurality of temperature measuring devices to measure the temperature of said mixture of first impure gas stream and second reactant containing gas streams before and after the gas flow in said reactor vessel;
e. a data analyzer for analyzing the temperature difference of said mixture of first impure gas stream and second reactant containing gas streams before and after the gas flow in said reactor vessel and controlling the flow of said first impure gas stream.
18. The system of claim 17 further comprising a plurality of flow controlling devices to control the flow of the first impure gas stream and second reactant containing gas stream.
19. The system of claim 17 further comprising a plurality of pressure gauges for measuring the flow of said first impure gas stream and second reactant containing gas stream.
20. The system of claim 17 wherein said reactor vessel comprises a catalyst bed for purifying the mixture of gases.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a semiconductor device comprising:
performing an operation test on a plurality of memory cells each accessed based on a row address and a column address;
generating error pattern information and error address information when a first defective memory cell is detected in the operation test;
each time one of a plurality of second defective memory cells different from the first defective memory cell is detected in the operation test, updating the error pattern information based on a relative arrangement relationship between the first and second defective memory cells and updating the error address information based on addresses of at least part of the first and second defective memory cells; and
replacing the first and second defective memory cells with respective redundant memory cells based on the error pattern information and the error address information,
wherein the error pattern information is updated from a first value to a second value if the first and second defective memory cells have either a same row address or a same column address,
wherein the error pattern information is updated from the second value to a third value if two of three defective memory cells consisting of the first defective memory cell and two of the second defective memory cells including a predetermined defective memory cell have a same row address, and two of the three defective memory cells including the predetermined defective memory cell have a same column address, and
wherein the error pattern information is updated from the third value to a fourth value if each of four defective memory cells consisting of the first defective memory cell and three of the second defective memory cells has either one of first and second row addresses and either one of first and second column addresses.
2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the semiconductor device includes a plurality of semiconductor chips packaged in a same package, and at least one of the semiconductor chips includes the plurality of memory cells.
3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the error pattern information and the error address information are generated and updated by an analysis circuit that is arranged on another one of the semiconductor chips.
4. A method of manufacturing a semiconductor device comprising:
performing an operation test on a plurality of memory cells each accessed based on a row address and a column address;
generating error pattern information and error address information when a first defective memory cell is detected in the operation test;
each time one of a plurality of second defective memory cells different from the first defective memory cell is detected in the operation test, updating the error pattern information based on a relative arrangement relationship between the first and second defective memory cells and updating the error address information based on addresses of at least part of the first and second defective memory cells; and
replacing the first and second defective memory cells with respective redundant memory cells based on the error pattern information and the error address information,
wherein the error pattern information is updated from a first value to a second value if the first and second defective memory cells have either a same row address or a same column address,
wherein the error pattern information is updated from the second value to a fifth value if three or more defective memory cells consisting of the first defective memory cell and two or more of the second defective memory cells coincide in either one of the row address and the column address, and
wherein the error address information associated with the error pattern information having the fifth value includes the one of the row address and column address of the three or more defective memory cells, a smallest address value of other of the row address and column address of the three or more defective memory cells, and a largest address value of the other of the row address and column address of the three or more defective memory cells.
5. A method of manufacturing a semiconductor device comprising:
performing a first operation test on a plurality of memory devices in a wafer state;
analyzing addresses of defective memory cells detected by the first operation test to identify first defective word lines and first defective bit lines;
replacing the first defective word lines and the first defective bit lines with first redundant word lines and first redundant bit lines in the wafer state, respectively;
dicing the wafer into individual memory chips;
packaging one or more semiconductor chips including at least one of the memory chips;
performing a second operation test on the packaged semiconductor device;
analyzing addresses of defective memory cells detected by the second operation test to identify second defective word lines and second defective bit lines; and
replacing the second defective word lines and the second defective bit lines with second redundant word lines and second redundant bit lines, respectively, wherein
the addresses of the defective memory cells detected by the second operation test are analyzed by an analysis circuit provided in the semiconductor device, and
the analysis circuit updating error pattern information and error address information each time the defective memory cell is detected, the error pattern information indicating a relative arrangement relationship between a plurality of defective memory cells, the error address information indicating the addresses of at least part of the plurality of defective memory cells.
6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the analysis circuit sets the error pattern information to a first value and sets the error address information to a value that includes a row address and a column address of the defective memory cell when a first defective memory cell is detected, and
when a second defective memory cell that coincides with the first defective memory cell in either one of the row address and column address is detected, the analysis circuit updates the error pattern information from the first value to a second value and updates the error address information to a value that includes the one of the row address and column address of the first and second defective memory cells, other of the row address and column address of the first defective memory cell, and the other of the row address and column address of the second defective memory cell.
7. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the memory chips include two or more memory chips and at least one control chip for controlling the memory chips, and
the analysis circuit is arranged in the control chip.
8. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the memory chip includes a plurality of redundant word lines that are usable at least as the first redundant word line and a plurality of redundant bit lines that are usable at least as the first redundant bit line,
different numbers are assigned to the respective plurality of redundant word lines,
different numbers are assigned to the respective plurality of redundant bit lines,
redundant word lines to which smaller numbers are assigned are preferentially used when the first defective word lines are replaced with the first redundant word lines,
redundant bit lines to which smaller numbers are assigned are preferentially used when the first defective bit lines are replaced with the first redundant bit lines,
redundant word lines to which greater numbers are assigned are preferentially used when the second defective word lines are replaced with the second redundant word lines, and
redundant bit lines to which greater numbers are assigned are preferentially used when the second defective bit lines are replaced with the second redundant bit lines.
9. A semiconductor device comprising:
a memory chip including a plurality of memory cells that include defective memory cells and redundant memory cells; and
a control chip stacked with the memory chip to control data read and write operations of the memory chip, the control chip including an analysis circuit,
wherein the analysis circuit of the control chip includes a plurality of fuse circuits to store a plurality of defective address information respectively indicative of the defective memory cells of the memory chip to generate replacing addresses, the replacing addresses causing the defective memory cells to be replaced respectively with ones of the redundant memory cells.
10. The semiconductor device as claimed in claim 9, wherein the analysis circuit of the control chip generates, when initially receiving the defective address information of one of the defective memory cells, error pattern information in response to the defective address information of the one of the defective memory cells and updates, when receiving the defective address information of another of the defective memory cells, the error pattern information in response to the defective address information of both of the one and another of the defective memory cells.
11. The semiconductor device as claimed in claim 10, wherein the control chip further includes an analysis memory including a register to store the error pattern information generated by the analysis circuit and the error pattern information stored in the register being overwritten when the error pattern information is updated by the analysis circuit.
12. The semiconductor device as claimed in claim 11, wherein the analysis memory of the control chip further includes one or more additional registers to store specified one or ones of the defective address information and the analysis circuit of the control chip generates the replacing addresses in response to both of the error pattern information stored in the register and the specified one or ones of the defective address information stored in the additional registers.
13. The semiconductor device as claimed in claim 9, wherein the memory cells of the memory chip further include additional defective memory cells and the memory chip further includes:
an additional fuse circuit storing additional replacing addresses, the additional replacing addresses causing the additional defective memory cells to be replaced respectively with additional ones of the redundant memory cells; and
a defective address latch circuit latching each of the replacing addresses and the additional replacing addresses.
14. The semiconductor device as claimed in claim 13, wherein one or more of the plurality of fuse circuits is to be programmed by an electric current and the additional fuse circuit of the memory chip is to be programmed by a laser beam.
15. The semiconductor device as claimed in claim 13, wherein the additional fuse circuit of the memory chip comprises an optical fuse circuit.
16. The semiconductor device as claimed in claim 9, wherein one or more of the plurality of fuse circuits comprises an electrical fuse circuit.