1. A multicell amplifier, comprising:
a) a first power divider unit which, in use, receives an input signal of the amplifier, divides the input signal into 2N subsignals, amplifies the 2N subsignals into first amplified signals and recombines the first amplified signals in two N-way power combiners to form two local output signals;
b) two further power divider units which, in use, take the two local output signals and divide the two local output signals into 4N subsignals, amplify the 4N subsignals into second amplified signals and recombine the second amplified signals to form three local output signals; and
c) two power combiner units which, in use, take the three local output signals and divide the three local output signals into 4N subsignals, amplify the 4N subsignals into third amplified signals and recombine the third amplified signals to provide an output signal of the amplifier.
2. A multicell amplifier, comprising:
a) a number of dividing units and combining units,
i) each dividing unit comprising a 2N-way divider for dividing an input signal into first and second sets of N phase-shifted signals, a first cell of N amplifying devices and a second cell of N amplifying devices connected to receive the respective first and second phase-shifted signal sets and provide respective sets of amplified phase-shifted signals, and first and second N-way combiners connected to receive the respective sets of amplified phase-shifted signals, the N-way combiners having outputs forming first and second outputs of the respective dividing unit, each of the combiners introducing phase shifts which are the reverse of phase shifts introduced by the divider, and
ii) each combining unit comprising first and second N-way dividers for dividing respective input signals into first and second sets of N phase-shifted signals, a first cell of N amplifying devices and a second cell of N amplifying devices connected to receive the respective first and second phase-shifted signal sets and provide respective sets of amplified phase-shifted signals, and a 2N-way combiner for combining the 2N amplified phase-shifted signals into an output signal of the combining unit, the combiner introducing phase shifts which are the reverse of phase shifts introduced by each divider;
b) a first dividing unit for receiving an input signal of the amplifier;
c) second and third dividing units connected to respective outputs of the first dividing unit;
d) a first combining unit having inputs connected to respective outputs of the second dividing unit;
e) a second combining unit having inputs connected to respective outputs of the third dividing unit; and
f) the first and second combining units having respective outputs combined to form an output of the amplifier.
3. The amplifier as claimed in claim 2, wherein an output of the second dividing unit and an output of the third dividing unit are combined to form a common output, and an input of the first combining unit and an input of the second combining unit are combined to form a common input, the common output being connected to the common input.
4. The amplifier as claimed in claim 3, wherein the common output is that of a 2N-way combiner providing a function of an N-way combiner in the second dividing unit and of an N-way combiner in the third dividing unit, and wherein the common input is that of a 2N-way divider providing a function of an N-way divider in the first combining unit and of an N-way divider in the second combining unit.
5. The amplifier as claimed in claim 4, wherein the number N in the first dividing unit corresponds to K cells, wherein the number N in the second and third dividing units corresponds to L cells, and wherein the number N in the first and second combining units corresponds to M cells.
6. The amplifier as claimed in claim 5, wherein K, L and M are all different and in ascending order.
7. The amplifier as claimed in claim 6, wherein the number N is the same in all units.
8. The amplifier as claimed in claim 2, wherein the amplifying devices are field effect transistors connected in common-source mode.
9. The amplifier as claimed in claim 2, wherein the amplifier is a monolithic amplifier on a substrate having an aspect ratio less than 1.5:1.
10. The amplifier as claimed in claim 2, wherein the phase-shifts in the various dividers and combiners are all approximately equal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for generating a first cipher (C_G0\u2014O1) containing a first private key (G0) of a first asymmetric cryptographical key pair (K0), the method comprising:
determining to generate the first cipher (C_G0\u2014O1) ;
generating on a computing device a second asymmetric cryptographical key pair (K1) based upon the determining, the second asymmetric cryptographical key pair (K1) comprising a second private key (G1) and a second public key (O1);
receiving a third private key (G2), wherein the third private key forms a third asymmetric cryptographical key pair (K2)together with a third public key (O2);
receiving a second cipher (C_G0\u2014O2), wherein the second cipher comprises the first private key (G0) following encryption with the third public key (O2);
decrypting the second cipher (C_G0\u2014O2) with the third private key (G2) to obtain the first private key (G0);
generating the first cipher (C_G0\u2014O1) by encrypting the first private key (G0) with the second public key (O1), wherein the generating the first cipher (C_G0\u2014O1) comprises encrypting the first private key (G0) obtained by decrypting the second cipher (C_G0\u2014O2)and
storing the first cipher (C_G0\u2014O1).
2. The method of claim 1, wherein the generating the second asymmetric cryptographical key pair (K1) comprises:
receiving a user input, and
generating the second asymmetric cryptographical key pair (K1) based upon the user input.
3. The method of claim 2, wherein:
the user input comprises a user identifier;
the generating the second asymmetric cryptographical key pair (K1) comprises:
calculating the second private key (G1) based upon a random value (z) and the user identifier; and
calculating the second public key (O1) from the second private key using an asymmetric cryptographical key generation method; and
the method further comprises storing the random value (z) in a data base.
4. The method of claim 3, further comprising:
receiving the user identifier, the first cipher (C_G0\u2014O1), and the random value (z);
calculating the second private key (G1) based upon the random value (z) and the user identifier;
decrypting the first cipher (C_G0\u2014O1) with the second private key (G1) to obtain the first private key (G0); and
decrypting data with the first private key (G0).
5. The method of claim 4, wherein:
the first private key (G0) is stored on a tangible portable data storage medium; and
the first private key (G0) is obtained from the first cipher (C_G0\u2014O1) without accessing the tangible portable data storage medium.
6. The method of claim 1, wherein:
the first private key (G0) is stored on a tangible portable data storage medium of a first user; and
the method further comprises storing the second asymmetric cryptographical key pair (K1) on a computing device of a second user.