What is claimed is:
1. A cylinder valve assembly with a check valve comprising:
a housing (4) which has an inlet bore (7), a stop valve chamber (9), a check valve chamber (41) and a valve-opening means accommodation portion (53);
the check valve chamber (41) provided with a check spring (43) and a chamber inlet (41a) which communicates with the inlet bore (7) through the stop valve chamber (9);
a check valve seat (44) formed around the chamber inlet (41a);
a check valve member (42) inserted into the check valve chamber (41) and resiliently pushed toward the check valve seat (44) by the check spring (43);
the valve-opening means accommodation portion (53) having a peripheral wall and formed at a position where it faces the check valve member (42) through the chamber inlet (41a);
a check valve member opening means (51) attached in the valve-opening means accommodation portion (53), the opening means (51) switching over by being pushed through a valve-opening actuation means (60) to a valve opening position (Y) where it advances toward the check valve chamber (41) and pushes the check valve member (42) for opening it, and, upon removal of the pushing force of the valve-opening actuation means (60), to a valve-opening cancellation position (X) where it retreats from the check valve chamber (41) and separates from the check valve member (42);
a lock means (55) made of a magnet and attached between the peripheral wall of the valve-opening means accommodation portion (53) and the check valve member opening means (51), the lock means (55) changing over between a lock position (L) where it limits an advancement of the check valve member opening means (51) from the valve-opening cancellation position (X) and a lock cancellation position (M) where it allows the advancement;
a lock cancellation means (61) formed from a magnetic body and provided in the valve-opening actuation means (60); and
at least one of the lock means (55) and the lock cancellation means (61) being made of a magnet, the lock means (55) changing over from the lock position (L) to the lock cancellation position (M) through a magnetic force produced between the lock means (55) and the lock cancellation means (61).
2. The cylinder valve assembly with the check valve as set forth in claim 1, wherein
the valve-opening actuation means (60) has a leading end portion at a position where it faces the check valve member opening means (51), and
the lock cancellation means (61) is formed from a magnet and disposed on the leading end portion of the valve-opening actuation means (60).
3. The cylinder valve assembly with the check valve as set forth in claim 2, wherein the check valve member opening means (51) has an outer peripheral surface, in which a lock means accommodation groove (54) is formed annularly,
an engaging groove (59) being formed in the peripheral wall of the valve-opening means accommodation portion (53) at a position where it opposes to the lock means accommodation groove (54) of the check valve member opening means (51) existing at the valve-opening position (X),
the lock means (55) being formed spherical and accommodated in the lock means accommodation groove (54), the lock means (59) partly invading the engaging groove (59) to come to the lock position (L).
4. The cylinder valve assembly with the check valve as set forth in claim 3, wherein
the lock means accommodation groove (54) is formed wider as it opens more outwardly and has its side walls inclined.
5. The cylinder valve assembly with the check valve as set forth in claim 2, wherein
the check valve member opening means (51) has a rear end on a side opposite to the check valve member (42) and an attaching recess (51a) is provided by concaving the rear end of the check valve member opening means (51),
the valve-opening actuation means (60) having its leading end portion attached to the attaching recess (51a).
6. The cylinder valve assembly with the check valve as set forth in claim 1, wherein a valve-opening cancellation spring (56) is arranged in the valve-opening means accommodation portion (53) and resiliently pushes the check valve member opening means (51) from the valve opening position (Y) to the valve-opening cancellation position (X).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of processing configuration data for a programmable device, the configuration data having a sequence of frames, the method comprising:
identifying bits in the sequence of frames as \u201cdon’t care\u201d bits that do not affect functionality of a design implemented in the programmable logic device;
comparing frames in the sequence of frames to identify at least one set of identical frame, where the \u201cdon’t care\u201d bits are deemed to result in matches; and
merging each of the at least one set of identical frames to produce a respective at least one merged frame, each of the at least merged frame being associated with a plurality of configuration memory addresses in the programmable device.
2. The method of claim 1, further comprising:
providing a compressed sequence of frames having the at least one merged frame and a portion of the sequence of frames.
3. The method of claim 2, further comprising:
loading the compressed sequence of frames into configuration memory of the programmable device, each of the at least one merged frame being written to the plurality of configuration memory addresses associated therewith.
4. The method of claim 3, wherein the programmable device comprises a field programmable gate array, and wherein each of the at least one merged frame is written to the configuration memory using a multi-frame write process.
5. The method of claim 1, wherein the \u201cdon’t care\u201d bits comprise at least one of: architectural \u201cdon’t care\u201d bits of the programmable device, design \u201cdon’t care\u201d bits of the programmable device, and bits associated with unused logic in the programmable device.
6. The method of claim 1, wherein the steps of identifying, comparing, and merging are performed by a computer system external to the programmable device.
7. A method of processing configuration data for a programmable device, the configuration data having a sequence of frames, the method comprising:
defining a set of nodes, each node in the set of nodes being associated with a frame in the sequence of frames, a mask that identifies the location of any \u201cdon’t care\u201d bits in the frame, and configuration memory address data associated with the programmable device;
defining a graph by computing arcs between respective pairs of nodes in the set of nodes, each of the pairs being associated with identical frames after ignoring any \u201cdon’t care\u201d bits; and
processing the graph to combine a portion of the set of nodes to produce a reduced set of nodes.
8. The method of claim 7, further comprising:
providing a compressed sequence of frames in accordance with the reduced set of nodes.
9. The method of claim 7, wherein the step of processing comprises:
(a) selecting an arc of the arcs;
(b) removing a first node and a second node in the pair of nodes associated with the selected arc from the graph;
(c) forming a new frame from the identical frames associated with the first node and the second node, the mask associated with the first node, and the mask associated with the second node;
(d) forming a new mask from the mask associated with the first node and the mask associated with the second node;
(e) forming new configuration memory address data from the configuration memory address data associated with the first node and the configuration memory address data associated with the second node; and
(f) adding a new node associated with the new frame, the new mask, and the new configuration memory address data to the graph.
10. The method of claim 9, wherein the step of processing further comprises:
(g) re-computing any other of the arcs associated with the first node or the second node with respect to the new node.
11. The method of claim 10, further comprising:
selecting at least one additional arc of the arcs; and
repeating steps (b) through (g) for the at least one additional selected arc.
12. The method of claim 9, wherein the selected arc is chosen such that, when the pair of nodes associated with the selected arc are removed form the graph, the fewest \u201cdon’t care\u201d bits are eliminated from the new frame.
13. Apparatus for processing configuration data for a programmable device, the configuration data having a sequence of frames, the apparatus comprising:
an identification unit identifying bits in the sequence of frames as \u201cdon’t care\u201d bits that do not affect functionality of a design implemented in the programmable device; and
a compressor unit for comparing frames in the sequence of frames to identify at least one set of identical frames, where the \u201cdon’t care\u201d bits are deemed to result in matches, and merging each of the at least one set of identical frames to produce a respective at least one merged frame, each of the at least merged frame being associated with a plurality of configuration memory addresses in the programmable device.
14. The apparatus of claim 13, further comprising:
a memory for storing a compressed sequence of frames having the at least one merged frame and a portion of the sequence of frames.
15. The apparatus of claim 14, wherein the memory is coupled to the programmable device for loading the compressed sequence of frames into configuration memory of the programmable device, each of the at least one merged frame being written to the plurality of configuration memory addresses associated therewith.
16. The apparatus of claim 15, wherein the programmable device comprises a field programmable gate array (FPGA), and wherein the FPGA is configured to write each of the at least one merged frame to the configuration memory using a multi-frame write process.
17. The apparatus of claim 13, wherein the compressor unit is coupled to the programmable device for loading the compressed sequence of frames into configuration memory of the programmable device, each of the at least one merged frame being written to the plurality of configuration memory addresses associated therewith.
18. The apparatus of claim 17, wherein the programmable device comprises a field programmable gate array (FPGA), and wherein the FPGA is configured to write each of the at least one merged frame to the configuration memory using a multi-frame write process.
19. The apparatus of claim 13, wherein the \u201cdon’t care\u201d bits comprise at least one of: architectural \u201cdon’t care\u201d bits of the programmable device, design \u201cdon’t care\u201d bits of the programmable device, and bits associated with unused logic in the programmable device.
20. The apparatus of claim 13, wherein the identification unit and the compressor unit comprise a portion of a computer system.