1. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows;
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage; and
a valve unit configured to restrict a flow of the water in the coolant passage.
2. The personal watercraft according to claim 1,
wherein the coolant passage includes an upstream passage located upstream of the engine in the water flow direction and a downstream passage located downstream of the engine; and
wherein the downstream passage is coupled to an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil.
3. The personal watercraft according to claim 1,
wherein the coolant passage includes an upstream passage located upstream of the engine in the water flow direction and a plurality of downstream passages located downstream of the engine; and
wherein the valve unit is configured to substantially open and close one of the plurality of downstream passages.
4. The personal watercraft according to claim 3,
wherein the downstream passage which is provided with the valve unit is coupled to a cylinder block passage provided in a cylinder block of the engine;
wherein the upstream passage, and the downstream passage which is not provided with the valve unit are coupled to a cylinder head passage provided in a cylinder head of the engine; and
wherein the cylinder block passage and the cylinder head passage are connected to each other.
5. The personal watercraft according to claim 1,
wherein the valve unit includes a valve bore formed in the coolant passage, a valve plug accommodated in the valve bore; and a downstream seat portion which is located on a downstream side of the valve bore and is configured to seat the valve plug thereon; and
wherein the valve plug is seated on the downstream seat portion to close a passage in the valve bore when a flow rate of the water flowing in the coolant passage is predetermined value or larger, and is away from the downstream seat portion when the flow rate of the water flowing in the coolant passage is smaller than the predetermined value.
6. The personal watercraft according to claim 5,
wherein the valve unit includes an upstream seat portion which is located on an upstream side of the valve bore and is configured to seat the valve plug thereon when a pressure of the water flowing in the coolant passage is smaller than a predetermined value; and
wherein the upstream seat portion is provided with a connecting portion which permits the water to flow in the valve bore with the valve plug seated on the upstream seat portion.
7. The personal watercraft according to claim 6,
wherein the valve plug is configured to drop by a gravitational force to be seated on the upstream seat portion.
8. The personal watercraft according to claim 6,
wherein the valve plug is configured to be subjected to a force applied from a biasing member disposed within the valve bore to be seated on the upstream seat portion.
9. The personal watercraft according to claim 1,
wherein the coolant passage includes an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of an engine oil;
an inlet passage coupled to an inlet port of the oil cooler passage;
an outlet passage coupled to an outlet port of the oil cooler passage; and
a bypass passage configured to directly couple the inlet passage to the outlet passage.
10. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows; and
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage;
wherein the coolant passage includes:
an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil;
an inlet passage coupled to an inlet port of the oil cooler passage;
an outlet passage coupled to an outlet port of the oil cooler passage; and
a bypass passage configured to directly couple the inlet passage to the outlet passage.
11. The personal watercraft according to claim 10, further comprising:
a bypass valve unit configured to restrict a flow of the water flowing in the bypass passage.
12. The personal watercraft according to claim 11, further comprising:
an actuator configured to drive the bypass valve unit; and
a controller configured to control the actuator;
wherein the controller is configured to control the actuator according to a temperature of the water flowing in the coolant passage.
13. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows; and
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage;
wherein the coolant passage includes an upstream passage located upstream of the engine in a water flow direction and a downstream passage located downstream of the engine; and
wherein the downstream passage is coupled to an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil.
14. The personal watercraft according to claim 13,
wherein a temperature of the water flowing into the oil cooler passage is higher than the temperature of the engine oil within the oil cooler when an engine speed of the engine is low; and wherein
the temperature of the water flowing into the oil cooler passage is lower than the temperature of the engine oil within the oil cooler when the engine speed of the engine is high.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory array comprising:
a plurality of addressable memory locations; and
a circuit to stage the data output from an addressable memory location so that different stages of the data from that addressable memory location are to be output at different times, wherein each stage is a field of the data stored at the memory location.
2. The memory array of claim 1, wherein the different stages are each output during a different clock cycle.
3. The memory array of claim 1, wherein the circuit further comprises a main array control block, and wherein the memory array is to output a first field that is stored at an address at an earlier stage than a second field that is stored at that address if the first field is stored closer to the main array control block than the second field.
4. The memory array of claim 1, wherein the circuit further comprises a main array control block, wherein a plurality of fields having different levels of time criticality are stored at an individual address, and wherein a more time critical field is stored closer to the main array control block than a less time critical field.
5. The memory array of claim 1, wherein the memory array has a plurality of sides, wherein the memory array has an address input port and a plurality of data output ports, and wherein the address input port is on a different side of the memory array than the data output ports.
6. The memory array of claim 1, wherein each addressable memory location comprises a plurality of memory cells, and wherein the memory array further comprises:
an address input port on a first side of the memory array;
a plurality of data output ports on a second side of the memory array; and
a plurality of paths that traverse from the address input port to a one of the memory cells and from that memory cell to a data output port, wherein each path traverses a line between the first side and the second side only once.
7. A memory array comprising:
a first bank comprising a plurality of memory cells;
an input port to receive an address that identifies a memory location, wherein each memory location comprises a plurality of subdivisions, wherein each subdivision comprises a plurality of said first bank memory cells; and
a stage delay circuit to cause each of the memory location subdivisions in the first bank that are identified by a particular address to output data during a different cycle of a clock than any other memory location subdivisions in the first bank that are identified by that address.
8. The memory array of claim 7, wherein the memory array further comprises a main array control block.
9. The memory array of claim 8, wherein memory location subdivisions in the first bank that are identified by a particular address are located at a different distances from the main array control block, and wherein the memory array is to output data stored in a first subdivision that is identified by that address before data stored in a second subdivision that is identified by that address if the first subdivision is located closer to the main array control block than the second subdivision.
10. The memory array of claim 8, wherein the memory array further comprises a second bank coupled to the main array control block, the second bank comprising a plurality of cells, wherein each of the subdivisions in the plurality of memory locations further comprises a plurality of said second bank memory cells, wherein the stage delay circuit is to cause each of the memory location subdivisions in the second bank that are identified by a particular address to output data during a different clock cycle than any other memory location subdivisions in the second bank that are identified by that address.
11. The memory array of claim 10, wherein the main array control block has a plurality of sides, and wherein the first bank is located on a different side of the main array control block than the second bank.
12. The memory array of claim 11, wherein a subdivision of a memory location in the first bank corresponds to a subdivision of that memory location in the second bank, and wherein the memory array outputs data from the corresponding subdivisions in the first bank and second bank during the same clock cycle.
13. The memory array of claim 7, wherein the memory array further comprises a plurality of data output ports, wherein the memory array has a plurality of sides, and wherein the input port and the plurality of data output ports are on opposite sides of the memory array.
14. A memory array comprising:
a main array control block to control the output of data items from the memory array for a plurality of addresses, wherein the main array control block has a plurality of sides;
a first bank of memory cells located on a first side of the main array control block, wherein the first bank is to store a first field of each of said data items; and
a second bank of memory cells located on a different side of the main array control block than the first bank, wherein the second bank is to store a second field of each of said data items.
15. The memory array of claim 14, wherein the memory array is to output the data for an individual address in different stages.
16. The memory array of claim 15, wherein data for a first stage for an individual memory address is output from both the first bank and the second bank.
17. The memory array of claim 14, wherein each data item comprises a plurality of fields, and wherein the memory array is to output a first field for a data item at an earlier stage than a second field for that data item if the first field is located closer to the main array control block than the second field.
18. The memory array of claim 14, wherein the memory array has a plurality of sides, wherein the memory array has an address input port and a plurality of data output ports, and wherein the address input port is on a different side of the memory array than the data output ports.
19. The memory array of claim 14, wherein for each individual address the memory array is to store a plurality of data fields having different levels of time criticality, and wherein a more time critical field is stored closer to the main array control block than a less time critical field.
20. A method comprising:
sending a request to a memory array to read from an address; and
receiving the data item stored at the address from the memory array, wherein the data item is output as a plurality of data fields, wherein the fields are output in stages, and wherein a most time critical field in the data item is output before a less time critical field in the data item.
21. The method of claim 20, wherein the method further comprises:
receiving a first field that is output at a first stage; and
beginning an operation using the first field before a second field is output at a second stage.
22. The method of claim 21, wherein the memory array is a trace cache.
23. The method of claim 21, wherein the memory array includes a main array control block, wherein the first field is stored in the memory array in a first subdivision of cells and the second field is stored in the memory array in second subdivision of cells, and wherein the main array control block is closer to the first subdivision of cells than the second subdivision of cells.