1. An apparatus comprising:
at least one processor configured to select a first gain for analog circuitry from among multiple discrete gain values and to select a second gain for a digital variable gain amplifier (DVGA), wherein the first gain maintains average power of a baseband signal within a predetermined range at an input of an analog-to-digital converter (ADC), and wherein the second gain maintains average power of an output signal from the DVGA at a reference power level; and
a memory coupled to the at least one processor.
2. The apparatus of claim 1, wherein the baseband signal is an OFDM waveform.
3. The apparatus of claim 1, wherein the predetermined range is at least a particular backoff below fullscale for the ADC, and wherein the particular backoff is selected based on a peak-to-average-power ratio (PAPR) of the baseband signal, power of interfering signals, or a combination thereof.
4. The apparatus of claim 1, wherein the reference power level is a particular backoff below fullscale for the DVGA, and wherein the particular backoff is selected based on a peak-to-average-power ratio (PAPR) of the output signal.
5. The apparatus of claim 1, wherein the at least one processor is configured to update an automatic gain control (AGC) loop based on power measurements and to select the first and second gains based on the AGC loop.
6. The apparatus of claim 5, wherein the at least one processor is configured to determine the average power of the baseband signal based on an output of the AGC loop and the discrete gain value for the first gain.
7. The apparatus of claim 1, wherein the at least one processor is configured to select a next higher discrete gain value, if available, for the first gain when the average power of the baseband signal is below a low threshold, and to select a next lower discrete gain value, if available, for the first gain when the average power of the baseband signal is above a high threshold.
8. The apparatus of claim 7, wherein the high and low thresholds are dependent on the discrete gain value for the first gain.
9. The apparatus of claim 7, wherein the high and low thresholds are defined based on ADC backoff and signal-to-quantization noise ratio (SQR) requirements.
10. The apparatus of claim 1, wherein the multiple discrete gain values are associated with multiple gain states, wherein each gain state except for a lowest gain state with a lowest analog gain is associated with a respective high threshold used for selecting a next lower gain state, and wherein each gain state except for a highest gain state with a highest analog gain is associated with a respective low threshold used for selecting a next higher gain state.
11. The apparatus of claim 10, wherein the high and low thresholds for the multiple gain states are defined to provide a predetermined amount of hysteresis in switching between gain states.
12. The apparatus of claim 10, wherein the high and low thresholds for the multiple gain states are programmable.
13. The apparatus of claim 1, wherein the at least one processor is configured
to determine a change in the first gain, and
to delay applying the change in the second gain such that the change is applied concurrently to the analog circuitry and the DVGA to reduce transients in the output signal.
14. A processor configured to select a first gain for analog circuitry from among multiple discrete gain values and to select a second gain for a digital variable gain amplifier (DVGA), wherein the first gain maintains average power of a baseband signal within a predetermined range at an input of an analog-to-digital converter (ADC), and wherein the second gain maintains average power of an output signal from the DVGA at a reference power level.
15. The processor of claim 14, and further configured to update an automatic gain control (AGC) loop based on power measurements and to select the first and second gains based on the AGC loop.
16. The processor of claim 14, and further configured to select a next higher discrete gain value, if available, for the first gain when the average power of the baseband signal is below a low threshold, and to select a next lower discrete gain value, if available, for the first gain when the average power of the baseband signal is above a high threshold.
17. A method comprising:
selecting a first gain for analog circuitry from among multiple discrete gain values, wherein the first gain maintains average power of a baseband signal within a predetermined range at an input of an analog-to-digital converter (ADC); and
selecting a second gain for a digital variable gain amplifier (DVGA), wherein the second gain maintains average power of an output signal from the DVGA at a reference power level.
18. The method of claim 17, further comprising:
updating an automatic gain control (AGC) loop based on power measurements, and wherein the first and second gains are selected based on the AGC loop.
19. The method of claim 17, wherein the selecting the first gain for the analog circuitry comprises
selecting a next higher discrete gain value, if available, for the first gain when the average power of the baseband signal is below a low threshold, and
selecting a next lower discrete gain value, if available, for the first gain when the average power of the baseband signal is above a high threshold.
20. An apparatus comprising:
means for selecting a first gain for analog circuitry from among multiple discrete gain values, wherein the first gain maintains average power of a baseband signal within a predetermined range at an input of an analog-to-digital converter (ADC); and
means for selecting a second gain for a digital variable gain amplifier (DVGA), wherein the second gain maintains average power of an output signal from the DVGA at a reference power level.
21. The apparatus of claim 20, further comprising:
means for updating an automatic gain control (AGC) loop based on power measurements, and wherein the first and second gains are selected based on the AGC loop.
22. The apparatus of claim 20, wherein the means for selecting the first gain for the analog circuitry comprises
means for selecting a next higher discrete gain value, if available, for the first gain when the average power of the baseband signal is below a low threshold, and
means for selecting a next lower discrete gain value, if available, for the first gain when the average power of the baseband signal is above a high threshold.
23. Computer-readable medium encoded with a computer program to:
select a first gain for analog circuitry from among multiple discrete gain values, wherein the first gain maintains average power of a baseband signal within a predetermined range at an input of an analog-to-digital converter (ADC); and
select a second gain for a digital variable gain amplifier (DVGA), wherein the second gain maintains average power of an output signal from the DVGA at a reference power level.
24. An apparatus comprising:
at least one processor configured to determine a logarithmic (log) error in an output signal level, to filter the log error with a loop filter to obtain a loop filter output, and to determine a first gain based on the loop filter output, wherein the first gain is used to correct the log error in the output signal level; and
a memory coupled to the at least one processor.
25. The apparatus of claim 24, wherein the at least one processor is configured to determine the log error using base 2 logarithm.
26. The apparatus of claim 24, wherein the at least one processor is configured to scale the log error with a loop gain to obtain a scaled log error and to filter the scaled log error with the loop filter to obtain the loop filter output.
27. The apparatus of claim 26, wherein the at least one processor is configured to use a first value for the loop gain in an acquisition mode and to use a second value for the loop gain in a tracking mode.
28. The apparatus of claim 24, wherein the at least one processor is configured to digitally multiply an input signal with the first gain to obtain an output signal and to determine the log error based on the output signal level and a reference power level.
29. The apparatus of claim 28, wherein the first gain comprises a first part that is a power of two and a second part that is in linear unit.
30. The apparatus of claim 24, wherein the at least one processor is configured to select one of multiple discrete gain values based on the loop filter output and to provide the selected discrete gain value as a second gain for analog circuitry.
31. A processor configured to determine a logarithmic (log) error in an output signal level, to filter the log error with a loop filter to obtain a loop filter output, and to determine a first gain based on the loop filter output, wherein the first gain is used to correct the log error in the output signal level.
32. The processor of claim 31, and further configured to digitally multiply an input signal with the first gain to obtain an output signal and to determine the log error based on the output signal level and a reference power level.
33. A method comprising:
determining a logarithmic (log) error in an output signal level;
filtering the log error with a loop filter to obtain a loop filter output; and
determining a first gain based on the loop filter output, wherein the first gain is used to correct the log error in the output signal level.
34. The method of claim 33, further comprising:
digitally multiplying an input signal with the first gain to obtain an output signal, and wherein the log error is determined based on the output signal level and a reference power level.
35. An apparatus comprising:
means for determining a logarithmic (log) error in an output signal level;
means for filtering the log error with a loop filter to obtain a loop filter output; and
means for determining a first gain based on the loop filter output, wherein the first gain is used to correct the log error in the output signal level.
36. The apparatus of claim 35, further comprising:
means for digitally multiplying an input signal with the first gain to obtain an output signal, and wherein the log error is determined based on the output signal level and a reference power level.
37. Computer-readable medium encoded with a computer program to:
determine a logarithmic (log) error in an output signal level;
filter the log error with a loop filter to obtain a loop filter output; and
determine a first gain based on the loop filter output, wherein the first gain is used to correct the log error in the output signal level.
38. An apparatus comprising:
at least one processor configured to update an automatic gain control (AGC) loop at a first update rate in an acquisition mode and to update the AGC loop at a second update rate in a tracking mode, wherein the second update rate is slower than the first update rate; and
a memory coupled to the at least one processor.
39. The apparatus of claim 38, wherein the at least one processor is configured to update the AGC loop multiple times for each OFDM symbol in the acquisition mode and to update the AGC loop once for each span of at least one OFDM symbol in the tracking mode.
40. The apparatus of claim 38, wherein the at least one processor is configured to update the AGC loop at OFDM symbol boundaries in the tracking mode.
41. The apparatus of claim 38, wherein the at least one processor is configured to start in the acquisition mode upon waking up from sleep and to remain in the acquisition mode for at least a predetermined number of AGC loop updates or until satisfaction of an exit condition prior to transitioning to the tracking mode.
42. The apparatus of claim 38, wherein the at least one processor is configured to derive power measurements based on a first predetermined number of samples in the acquisition mode, to derive power measurements based on a second predetermined number of samples in the tracking mode, wherein the second predetermined number is larger than the first predetermined number, and to update the AGC loop with the power measurements.
43. The apparatus of claim 38, wherein the at least one processor is configured to update the AGC loop with a first loop gain value in the acquisition mode and to update the AGC loop with a second loop gain value in the tracking mode.
44. A processor configured to update an automatic gain control (AGC) loop at a first update rate in an acquisition mode and to update the AGC loop at a second update rate in a tracking mode, wherein the second update rate is slower than the first update rate.
45. The processor of claim 44, and further configured to update the AGC loop multiple times for each OFDM symbol in the acquisition mode and to update the AGC loop once for each span of at least one OFDM symbol in the tracking mode.
46. The processor of claim 44, and further configured to derive power measurements based on a first predetermined number of samples in the acquisition mode, to derive power measurements based on a second predetermined number of samples in the tracking mode, wherein the second predetermined number is larger than the first predetermined number, and to update the AGC loop with the power measurements.
47. A method comprising:
updating an automatic gain control (AGC) loop at a first update rate in an acquisition mode; and
updating the AGC loop at a second update rate in a tracking mode, wherein the second update rate is slower than the first update rate.
48. The method of claim 47, wherein the updating the AGC loop at the first update rate in the acquisition mode comprises updating the AGC loop multiple times for each OFDM symbol in the acquisition mode, and wherein the updating the AGC loop at the second update rate in the tracking mode comprises updating the AGC loop once for each span of at least one OFDM symbol in the tracking mode.
49. The method of claim 47, further comprising:
deriving power measurements based on a first predetermined number of samples in the acquisition mode;
deriving power measurements based on a second predetermined number of samples in the tracking mode, wherein the second predetermined number is larger than the first predetermined number; and
updating the AGC loop with the power measurements.
50. An apparatus comprising:
means for updating an automatic gain control (AGC) loop at a first update rate in an acquisition mode; and
means for updating the AGC loop at a second update rate in a tracking mode, wherein the second update rate is slower than the first update rate.
51. The apparatus of claim 50, wherein the means for updating the AGC loop at the first update rate in the acquisition mode comprises means for updating the AGC loop multiple times for each OFDM symbol in the acquisition mode, and wherein the means for updating the AGC loop at the second update rate in the tracking mode comprises means for updating the AGC loop once for each span of at least one OFDM symbol in the tracking mode.
52. The apparatus of claim 50, further comprising:
means for deriving power measurements based on a first predetermined number of samples in the acquisition mode;
means for deriving power measurements based on a second predetermined number of samples in the tracking mode, wherein the second predetermined number is larger than the first predetermined number; and
means for updating the AGC loop with the power measurements.
53. Computer-readable medium encoded with a computer program to:
update an automatic gain control (AGC) loop at a first update rate in an acquisition mode, and
update the AGC loop at a second update rate in a tracking mode, wherein the second update rate is slower than the first update rate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A die assembly for use on a press and adapted to form a plurality of features on a strip of material, said die assembly comprising:
a first die section supported on the press and having a first tooling surface for forming a first feature; and,
a second die section longitudinally spaced from said first die section, said second die section supported on the press and capable of at least lateral movement relative to said first die section and to the longitudinal spacing, and said second section having second and third tooling surfaces, said second tooling surface for engaging the first feature and at least laterally displacing the second die section transverse to the longitudinal spacing, and said third tooling surface for forming a second feature.
2. A die assembly according to claim 1, wherein said first and second die sections each respectively include upper and lower die portions.
3. A die assembly according to claim 2 further comprising an upper die shoe and a lower die shoe in spaced relation to one another and supported on the press, said first and second die sections being disposed between said upper and lower die shoes.
4. A die assembly according to claim 3, wherein said first upper die portion is fixedly secured on said upper die shoe, said first lower die portion is fixedly secured on said lower die shoe in alignment with said first upper die section, and said second die section is moveably supported between said upper and lower die shoes.
5. A die assembly according to claim 4 further comprising a wear plate disposed between said second die section and one of said upper and lower die shoes facilitating sliding movement therebetween.
6. A die assembly according to claim 4, wherein said second die section includes an alignment member interconnecting said second upper die portion and said second lower die portion.
7. A die assembly according to claim 4 further comprising a plurality of retaining members disposed on one of said upper and lower die shoes to thereby limit the movement of said second die section.
8. A die assembly according to claim 1, wherein said at least lateral movement includes a transverse displacement component and a longitudinal displacement component.
9. A die assembly adapted to form first and second substantially concentric features on a strip of material, said die assembly comprising:
a first die section having first upper and lower die portions with corresponding first upper and lower tooling surfaces for forming the first feature; and,
a second die section longitudinally spaced from said first die section, said second die section adapted for radial movement relative to the first feature and to the longitudinal spacing, said second die section having second upper and lower die portions with corresponding second upper and lower tooling surfaces for forming the second feature, and one of said second upper and lower die sections including a third tooling surface for engaging the first feature to thereby radially locate said second die section transverse to the longitudinal spacing.
10. A die assembly according to claim 9, wherein said second die section includes a pilot extending from one of said second upper and lower die portions and said third tooling surface is disposed along said pilot.
11. A die assembly according to claim 9, wherein the first feature includes a side wall and said third tooling surface engages the side wall to locate said second die section relative thereto.
12. A die assembly according to claim 11, wherein the side wall is substantially cylindrical and said third tooling surface includes a substantially cylindrical portion dimensioned to be received within the side wall.
13. A die assembly according to claim 9, wherein the second feature is a substantially circular peripheral wall, said second upper die portion includes a punch having a substantially circular second upper tooling surface, and said second lower die portion includes a die ring having a substantially circular second lower tooling surface.
14. A die assembly according to claim 9, wherein said first feature has an approximate circular cross-section shape and said second tooling surface is adapted to engage said first feature and radially displace said second die section relative to said first feature, said radial displacement including a transverse displacement component and a longitudinal displacement component.
15. A method of forming first and second features on a strip of material, said method comprising steps of:
a) providing a first die section having a first tooling surface and a second die section longitudinally spaced from said first die section and having second and third tooling surfaces, said second die section being at least laterally displaceable relative to said first die section and to the longitudinal spacing;
b) providing the strip of material and advancing a portion of the strip of material into a first position adjacent said first tooling surface of said first die section;
c) forming a first feature on the strip of material using said first tooling surface;
d) advancing the strip of material into a second position such that the first feature is adjacent said second tooling surface;
e) engaging said second tooling surface with the first feature to displace said second die section and thereby locate said third tooling surface relative to said first feature and transverse to the longitudinal spacing; and
f) forming a second feature on the strip of material using said third tooling surface.
16. A method according to claim 15, wherein said first die section has first upper and lower die portions and said second die section has second upper and lower die portions, said first and second upper die portions and said first and second lower die portions being displaceable toward one another in a closing stroke and being displaceable away from one another in an opening stroke, and steps e) and f) being performed on the same closing stroke.
17. A method according to claim 15, wherein the strip of material is substantially stationary in step e).
18. A method according to claim 15, wherein step c) includes forming the first feature by one of drawing, coining, blanking, and breaking said strip of material.
19. A method according to claim 15, wherein step f) includes forming the second feature by one of drawing, coining, blanking, and breaking said strip of material.
20. A method according to claim 15, wherein the first feature formed in step c) is a cup having a side wall, said second die section includes a pilot adapted to be received within the cup and engage side wall, and step e) includes at least partially extending said pilot at least partially into said cup to engage the side wall and position said second die section in relation thereto.
21. A method according to claim 15, wherein step f) includes blanking a workpiece from the strip of material that includes the first and second features.
22. A method according to claim 21, wherein said step of blanking a workpiece includes substantially simultaneously forming the second feature.