1. A ball screw assembly, comprising:
a screw shaft having a spiral rolling groove formed on an outer surface thereof;
a nut having a spiral load rolling groove formed on an inner surface thereof, the screw shaft coupled through the nut, the rolling groove aligning with the load rolling groove, and the rolling groove and the load rolling groove jointly defining a raceway;
a plurality of balls disposed between the rolling groove of the screw shaft and the load rolling groove of the nut; and
two wipers respectively configured on two opposite sides of the nut and coupled with the rolling groove, wherein each wiper comprises:
a ring having a plurality of dust discharge grooves formed on an inner surface thereof and the inner surface of the ring substantially abuts the outer surface of the screw shaft; and
a plurality of wiping protrusions extended from the inner surface of the ring and each wiping protrusion arranged between any two adjacent dust discharge grooves;
wherein the wiping protrusions abut and are arranged in the rolling groove of the screw shaft, and the wiping protrusions of the wipers are arranged within a single pitch of the screw shaft.
2. The ball screw assembly as claimed in claim 1, wherein at least one of the plurality of dust discharge grooves is formed on the inner surface of the ring from a distal end of the ring to a portion between two adjacent wiping protrusions.
3. The ball screw assembly as claimed in claim 1, wherein each wiping protrusion has an elongated shape, and each cross-sectional area of the wiping protrusion along the longitudinal direction is identical.
4. The ball screw assembly as claimed in claim 1, wherein each ring has a positioning rim having two opposite ends, a main portion extended from one end of the positioning rim, and an extending wall extended form another end of the positioning rim, the wiping protrusions of each wiper extend from the inner side of the main portion to the inner side of the extending wall, and the extending wall of each wiper correspondingly extends from the wiping protrusions.
5. The ball screw assembly as claimed in claim 1, further comprising two end caps coupled to the screw shaft, the end caps are respectively configured on the two opposite sides of the nut, the end caps are respectively assembled with the wipers, and each end surface of the end cap exposed from the nut is formed with a plurality of concaved dust discharge outlets.
6. The ball screw assembly as claimed in claim 5, wherein the dust discharge outlets of each end cap respectively align with the dust discharge grooves of each wiper, and each dust discharge outlet and the corresponding dust discharge groove defined a dust discharge passage.
7. A wiper coupled to a rolling groove of a screw shaft, comprising:
a ring having a plurality of dust discharge grooves formed on an inner surface thereof, and the inner surface of the ring substantially configured to abut an outer surface of the screw shaft; and
a plurality of wiping protrusions extended from the inner surface of the ring and each wiping protrusion arranged between any two adjacent dust discharge grooves,
wherein when the wiper is coupled to the rolling groove of the screw shaft, the wiping protrusions abut and are arranged in the rolling groove of the screw shaft, and the wiping protrusions of the wipers are arranged within a single pitch of the screw shaft.
8. The ball screw assembly as claimed in claim 7, wherein at least one of the plurality of dust discharge grooves is formed on the inner surface of the ring from a distal end of the ring to a portion between two adjacent wiping protrusions.
9. The ball screw assembly as claimed in claim 7, wherein each wiping protrusion has an elongated shape, and each cross-sectional area of the wiping protrusion along the longitudinal direction is identical.
10. The ball screw assembly as claimed in claim 7, wherein each ring has a positioning rim, a main portion extended from one end of the positioning rim, and an extending wall extended form another end of the positioning rim, the wiping protrusions of each wiper extend from the inner side of the main portion to the inner side of the extending wall, and the extending wall of each wiper correspondingly extends from the wiping protrusions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processing apparatus in an integrated circuit, comprising:
a point-to-point data streaming interface;
a first arithmetic logic unit (ALU) circuitry having at least one input port;
a second ALU circuitry having at least one input port, wherein said second ALU circuitry processes branches;
a register file; and
multiplexer logic configured to selectively couple said register file and said point-to-point data streaming interface to said at least one input port of said first ALU circuitry and said at least one input port of said second ALU circuitry.
2. The apparatus of claim 1, further comprising:
a streaming interface circuit having at least one register in respective communication with said at least one input port of said first ALU circuitry.
3. The apparatus of claim 2, further comprising:
at least one first-in-first-out circuit (FIFO) in respective communication with said at least one register.
4. The apparatus of claim 3, wherein said first ALU circuitry is configured to read data from said at least one register in response to an instruction, and wherein new data is automatically loaded into said at least one register from said at least one FIFO.
5. The apparatus of claim 3, wherein said first ALU circuitry is configured to read data from said at least one register in response to an instruction, and wherein new data is loaded into said at least one register in response to state of at least one bit in said instruction.
6. The apparatus of claim 2, wherein said streaming interface circuit further comprises:
at least one shadow register respectively coupled to said at least one register.
7. The apparatus of claim 1, further comprising:
an instruction cache; and
a program memory, in communication with said instruction cache, for storing a set of instructions comprising a program.
8. The apparatus of claim 1, further comprising:
a program counter for storing a pointer to a next instruction to be executed in a program; and
automatic loop circuitry for comparing said pointer to a length of said program and for automatically resetting said program counter in response to said pointer equaling said length.
9. The apparatus of claim 1, wherein said first ALU circuitry comprises branch logic for processing instructions from a program having a branch field, said branch field including a pointer to a next instruction in said program to be executed.
10. The apparatus of claim 1, wherein said point-to-point data streaming interface and said first ALU circuitry is disposed within a processor embedded within said integrated circuit.
11. The apparatus of claim 1, wherein said integrated circuit comprises a field programmable gate array (FPGA).
12. A processing apparatus in an integrated circuit, comprising:
a point-to-point data streaming interface;
a program counter for storing a first pointer to a next instruction to be executed in a program;
a first arithmetic logic unit (ALU) circuitry having branch logic for processing instructions from said program, each of said instructions having a branch field, said branch field of at least one of said instructions including a second pointer to said next instruction in said program to be executed, wherein said first ALU circuitry has at least one input port;
a second ALU circuitry having at least one input port;
a register file;
first multiplexer logic for selectively providing said second pointer to said program counter; and
second multiplexer logic configured to selectively couple said register file and said point-to-point data streaming interface to said at least one input port of said first ALU circuitry and said at least one input port of said second ALU circuitry.
13. The apparatus of claim 12, further comprising:
a streaming interface circuit having at least one register in respective communication with said at least one input port of said first ALU circuitry.
14. The apparatus of claim 13, further comprising:
at least one first-in-first-out circuit (FIFO) in respective communication with said at least one register.
15. The apparatus of claim 12, further comprising:
an instruction cache; and
a program memory, in communication with said instruction cache, for storing a
set of instructions comprising a program.
16. The apparatus of claim 12, further comprising:
automatic loop circuitry for comparing said first pointer to a length of said program and for automatically resetting said program counter in response to said first pointer equaling said length.
17. The apparatus of claim 12, wherein said program counter, said first ALU circuitry, and said first multiplexer logic are disposed within a processor embedded within said integrated circuit.
18. In a processing block in an integrated circuit, a method, comprising:
loading input data to at least one first register via a point-to-point streaming interface;
receiving an instruction from a program;
reading said input data at arithmetic logic unit (ALU) circuitry from said at least one first register;
providing output data from said ALU circuitry to at least one second register;
sending said output data from said at least one second register over said point-to-point streaming interface;
reading another input data at another ALU circuitry from said at least one first register; and
processing, by the other ALU circuitry, the other input data, wherein the other input data includes a branch instruction.