1. A charge pump comprising a plurality of serially connected cells for pumping and transferring charge along a series of nodes between the cells, each cell including:
a) a charge transfer diode connected between adjacent nodes and responsive to an increasing charge at one node in response to a first clock, \u03c61, or a second anti-phase second clock, \u03c62,
b) a charge transfer transistor connected between the adjacent nodes in parallel with the charge transfer diode and responsive to a third clock, \u03c63, within the period of clock \u03c61 or to a fourth clock \u03c64 within the period of clock \u03c62,
c) a recovery transistor for equalizing charge on the control terminal of the charge transfer transistor to charge on the input node during a recovery period, and
d) a pre charge diode coupling an input node to a control terminal of the charge transfer transistor to facilitate the conductance of the charge transfer transistor in response to the third clock (\u03c63) or the fourth clock (\u03c64),
whereby each charge transfer diode transfers charge from one node to a next node in response to one of said first and second clocks (\u03c61 or \u03c62) and each charge transfer transistor transfers residual trapped charge at the one node to the next node while the charge transfer diode is conducting charge.
2. The charge pump as defined by claim 1 wherein each diode comprises a diode NMOSFET and each charge transfer transistor comprises a NMOSFET.
3. A method of increasing efficiency in charge transfer in a charge pump having a plurality of serially connected diodes which sequentially respond to anti-phase pumping clocks (\u03c61, \u03c62) comprising the steps of:
a) providing for each diode a charge transfer transistor in parallel therewith between two adjacent nodes,
b) driving the charge transfer transistor to conduction during a time when the parallel diode is conducting, thereby transferring any residual trapped charge at one node through the charge transfer transistor to the next node,
c) coupling the control terminal of the charge transfer transistor to an input node in response to charge on an output node to thereby equalize charge on the control terminal and on the input node during a recovery period, and
d) precharging a control terminal of the charge transfer transistor to facilitate the conductance of the charge transfer transistor.
4. The method as defined by claim 3 wherein each diode comprises a diode connected NMOSFET and each charge transfer transistor comprises a NMOSFET.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
a plurality of processing elements;
a nearest neighbor communication network between at least some of the processing elements. The nearest neighbor network including storage registers for storing data transfer information; and
a second communication network, separate from the nearest neighbor network, the second communication network including at least two coupled switches also coupled to the nearest neighbor network
2. An integrated circuit according to claim 1, further comprising:
an internal communication network having programmatically selected inputs for sending data to individual execution units within the processing elements.
3. An integrated circuit according to claim 2, wherein an output of an individual execution unit may be coupled to an input of another individual execution unit.
4. An integrated circuit according to claim 2, wherein an output of an individual execution unit may be coupled to an input of the same individual execution unit through a crossbar switch.
5. An integrated circuit according to claim 2. further comprising one or more protocol registers in a data path of the internal communication network.
6. An integrated circuit according to claim 1, further comprising:
a third communication network including at least two coupled switches also coupled to the second communication network.
7. An integrated circuit according to claim 6 in which the switches of the second communication network and the switches of the third communication network both include data storage registers.
8. An integrated circuit, comprising:
a plurality of processor groups arranged in a regular repeating pattern in an available space;
a plurality of first communication paths each contained within a respective one of the plurality of processor groups;
a plurality of nearest neighbor communication paths each coupled between adjacent pairs of the plurality of processor groups; and
a plurality of second communication paths coupled between selected of the adjacent pairs of the plurality of processors, the second communication paths including a first set of switches; wherein data is stored and transfers through registers along at least one of the communication paths.
9. An integrated circuit according to claim 8 in which the first set of switches is dynamically configurable.
10. An integrated circuit according to claim 9 in which the first communication paths comprises a crossbar switch.
11. An integrated circuit according to claim 8, farther comprising:
a plurality of third communication paths coupled between selected of the first set of switches of the plurality of second communication path, and coupled between a second set of switches within the plurality of third communication paths.
12. An integrated circuit of claim 11 in which a first processor in a first of the plurality of processor groups can communicate to a second processor in a second of the plurality of processor groups through the one of the nearest neighbor communication paths, through one of the second communication paths, and through one of the third communication paths.
13. An integrated circuit of claim 8 in which at least one of the communication paths comprises a pair of unidirectional communication paths configured in opposite directions.
14. An integrated circuit of claim 13 in which each of the unidirectional communication paths includes forward protocol data and reverse protocol data.
15. An integrated circuit of claim 8 in which at least two of the first set of switches is connected by more than one separate data path in each direction.
16. A method of transferring data within an integrated circuit, comprising:
configuring an inter-process group communication network to connect an output from a first processor in a first group of processors to an input of a second processor in the first group of processors;
configuring a nearest neighbor communication network to connect an output from the first processor in the first group of processors to an input of a first processor in a second group of processors; and
configuring a second communication network that is separate from the nearest neighbor communication network to connect an output from a second processor in the first group of processors to an input of a second processor in the second group of processors.
17. The method of claim 16 in which configuring an inter-processor group communication network comprises writing data to a register.
18. The method of claim 16 in which configuring a second communication network comprises writing data to one or more programmable switches included within the second communication network.
19. The method of claim 16, further comprising sending data through at least one data register along the nearest neighbor communication network.
20. The method of claim 19, further comprising sending reverse protocol data through the at least one data register.