What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a first active region provided in a surface of said semiconductor substrate and having a second conductivity type which is different from said first conductivity type;
a second active region provided in the surface of said semiconductor substrate at a distance from said first active region and having said second conductivity type;
a control electrode provided on the surface of said semiconductor substrate in a part interposed between said first and second active regions; and
a buried channel layer provided in said semiconductor substrate under said control electrode and having said second conductivity type, said buried channel layer being in contact with both of said first and second active regions;
said semiconductor substrate and said first active region constituting a photodiode which is part of a solid-state image sensor;
said control electrode and said first and second active regions constituting a transistor which is part of said solid-state image sensor; and
said buried channel layer having a lower impurity concentration than said first and second active regions.
2. The semiconductor device according to claim 1, further comprising
a third active region having said first conductivity type and provided in the surface of said first active region,
wherein said buried channel layer has a larger depth than said third active region from the surface of said semiconductor substrate.
3. The semiconductor device according to claim 1,
wherein said second active region is absent, and instead, said buried channel layer is extended also in the region where said second active region would reside if present.
4. The semiconductor device according to claim 1, further comprising
an element isolation insulating layer provided in the surface of said semiconductor substrate and having an edge extending along a periphery of said second active region,
wherein said second active region is provided in said semiconductor substrate with its said periphery spaced at a certain distance from said edge of said element isolation insulating layer.
5. The semiconductor device according to claim 1,
wherein said buried channel layer extends also in the part where said first active region is provided and overlaps said first active region, and
in said first active region and its vicinity, the depth of said buried channel layer from the surface of said semiconductor substrate at least reaches the depth of said first active region from the surface of said semiconductor substrate.
6. The semiconductor device according to claim 5,
wherein said buried channel layer extends also in the part where said second active region is provided and overlaps said second active region, and
in said second active region and its vicinity, said buried channel layer has a smaller depth from the surface of said semiconductor substrate than in said first active region and its vicinity.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated device comprising:
a first circuit having an input and an output, the input of the first circuit configured to receive an input signal and provide a first signal on the output of the first circuit;
a second circuit having an input and an output, the input of the second circuit configured to receive the input signal and provide a second signal on the output of the second circuit; and
a third circuit having a first input configured to receive the first signal and a second input configured to receive the second signal, the third circuit configured to combine the first signal and the second signal into a modulator drive output signal provided on an output of the third circuit,
wherein the second signal is complementary to the first signal, and
wherein the third circuit comprises a current source and a resistor, the current source cooperating with the resister to provide a bias signal, the third circuit configured to combine the bias signal, and the first signal and the second signal into the modulator drive output signal provided on the output of the third circuit.
2. The integrated circuit of claim 1, wherein the input signal is a differential signal and the modulator drive output signal is a differential modulator drive output signal.
3. The integrated device of claim 1, wherein the input signal is a single-ended signal and the modulator drive output signal is a single-ended modulator drive output signal.
4. The integrated device of claim 1, wherein the first circuit cooperates with the third circuit, such that the first signal is a high-pass response of the input signal having a first cutoff frequency, and the second circuit cooperates with the first circuit and the third circuit, such that the second signal is a low-pass response of the input signal having a second cutoff frequency.
5. The integrated device of claim 4, wherein the first cutoff frequency is substantially equal to the second cutoff frequency.
6. The integrated circuit of claim 1, wherein the first signal has a first frequency response and the second signal has a second frequency response which does not overlap the first frequency response.
7. The integrated circuit of claim 1, wherein the first signal has a first amplitude and the second signal has a second amplitude substantially the same as the first amplitude.
8. The integrated device of claim 1, wherein the current source is a programmable current source, such that the bias signal is programmable.
9. The integrated device of claim 8, wherein the programmable current source is controlled by a digital communication interface.
10. The integrated device of claim 9, wherein the digital communication interface is a 3-wire Serial Peripheral Interface or a 4-wire Serial Peripheral Interface.
11. The integrated device of claim 1, wherein the modulator is an electro-absorption modulator.
12. The integrated device of claim 11, wherein the first, second and third circuits are one of a plurality of modulated drive circuits provided on the single substrate.
13. The integrated device of claim 1, wherein the modulator is a Mach-Zehnder modulator.
14. The integrated device of claim 1, wherein the first, second and third circuits are provided on a single substrate.
15. An integrated device comprising:
a first circuit having an input and an output, the input of the first circuit configured to receive an input signal and provide a first signal on the output of the first circuit;
a second circuit having an input and an output, the input of the second circuit configured to receive the input signal and provide a second signal on the output of the second circuit; and
a third circuit having a first input configured to receive the first signal and a second input configured to receive the second signal, the third circuit configured to combine the first signal and the second signal into a modulator drive output signal provided on an output of the third circuit,
wherein the second signal is complementary to the first signal,
wherein the input signal is a differential signal and the modulator drive output signal is a differential modulator drive output signal, and
wherein the differential modulator drive output signal includes a first differential modulator drive output signal and a second differential modulator drive output signal, the third circuit further comprising a first current source coupled to the first output signal and a second current source coupled to the second output signal, the first current source providing a first bias signal and the second current source providing a second bias signal, the first differential modulator drive output signal comprising the first bias signal and the second differential modulator drive output signal comprising the second bias signal.
16. The integrated device of claim 15, wherein the first current source is a first programmable current source and the second current source is a second programmable current source.
17. The integrated device of claim 16, wherein the first programmable current source and the second programmable current source are controlled via a digital communication interface.
18. The integrated device of claim 17, wherein the digital communication interface is a 3-wire Serial Peripheral Interface or a four-wire Serial Peripheral Interface.