1. A public-key decryption process, comprising:
receiving from a sender (1) a public key of a key pair that is used for a single message, and (2) a second value s of a digital signature that was generated using the key pair, the digital signature comprising a first value r and the second value s;
calculating the first value r of the digital signature using the public key; and
validating the digital signature based upon the calculated first value r and the received second value s.
2. The public-key decryption process of claim 1, wherein a ciphertext message that was encrypted using the key pair is also received from the sender.
3. The public-key decryption process of claim 2, wherein validating the digital signature comprises hashing a plaintext message that is encrypted within the ciphertext message.
4. The public-key decryption process of claim 1, wherein the key pair was produced by:
generating a private key x; and
calculating the public key X=xG in a finite cyclic group having G as a generator.
5. The public-key decryption process of claim 4, the process comprising decrypting a ciphertext message received from the sender into a plaintext message by:
generating a secret key K=bX; and
decrypting the ciphertext message using the secret key K to generate the plaintext message.
6. The public-key decryption process of claim 5, wherein the sender used the private key x as a signature private key and used the public key X as a signature public key to generate the digital signature.
7. The public-key decryption process of claim 4, the process comprising decrypting a ciphertext message received from the sender into a plaintext message by:
generating a secret key K by calculating one of: bX, bxG, xbG, and xB; and
decrypting the ciphertext message using the generated secret key K.
8. The public-key decryption process of claim 1 implemented in a wireless communication system,
wherein at least a two stage public-key decryption process is used,
wherein a first stage includes key establishment and the second stage includes decryption, and
wherein decrypting a plaintext message and validating the digital signature are performed during the second stage.
9. The public-key decryption process of claim 1, further comprising:
at a sender,
generating a sender private key a; and
calculating a sender public key A=aG, where G is a generator;
and at a receiver,
generating a receiver private key b; and
calculating a receiver public key B=bG,
wherein the sender obtains an authentic copy of the receiver public key B and the receiver obtains an authentic copy of the sender public key A.
10. A communication device, comprising:
a computer-readable memory encoded with software instructions; and wherein:
the communication device is configured to receive from a sender (1) a public key of a key pair that is used for a single message, and (2) a second value s of a digital signature that was generated using the key pair, the digital signature comprising a first value r and the second value s;
the communication device is configured to calculate the first value r of the digital signature using the public key; and
the communication device is configured to validate the digital signature based upon the calculated first value r and the received second value s.
11. The communication device of claim 10, wherein the communication device is further configured to hash a plaintext message encoded within a ciphertext received from the sender when validating the digital signature.
12. The communication device of claim 10, wherein the communication device is further configured to generate a secret key K=bX where b is a receiver private key; and wherein the communication device is further configured to decrypt a ciphertext message using the secret key K.
13. The communication device of claim 10, wherein the communication device is further configured to generate a secret key K by calculating one of: bX, bxG, xbG, and xB where b is a receiver private key, B is a receiver public key, x is a private key of the key pair that is used for a single message and G is a generator; and wherein the communication device is further configured to decrypt a ciphertext message using the secret key K.
14. The communication device of claim 10, wherein the communication device is further configured to:
generate a receiver private key b;
calculate a receiver public key B=bG, where G is a generator; and
obtain an authentic copy of the sender public key A.
15. A wireless device for decrypting data, comprising:
a data processor;
a computer-readable memory encoded with instructions for commanding the data processor to execute steps including:
receiving from a sender (1) a public key of a key pair that is used for a single message, and (2) a second value s of a digital signature that was generated using the key pair, the digital signature comprising a first value r and the second value s;
calculating the first value r of the digital signature using the public key; and
validating the digital signature based upon the calculated first value r and the received second value s.
16. The wireless device of claim 15, wherein the computer-readable memory is further encoded with instructions for commanding the data processor to execute steps including hashing a plaintext message encoded within a ciphertext message received from the sender when validating the digital signature.
17. The wireless device of claim 16, wherein the computer-readable memory is further encoded with instructions for commanding the data processor to execute steps including:
generating a secret key K=bX where b is a receiver private key; and
decrypting the ciphertext message using the secret key K.
18. The wireless device of claim 16, wherein the computer-readable memory is further encoded with instructions for commanding the data processor to execute steps including:
generating a secret key K by calculating one of: bX, bxG, xbG, and xB where b is a receiver private key, B is a receiver public key, x is a private key of the key pair that is used for a single message and G is a generator; and
decrypting the ciphertext message using the secret key K.
19. The wireless device of claim 15, wherein the computer-readable memory is further encoded with instructions for commanding the data processor to execute steps including:
generating a receiver private key b;
calculating a receiver public key B=bG, where G is a generator; and
obtaining an authentic copy of the sender public key A.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating an NROM memory cell array, the method comprising:
introducing dopant at a top side of a semiconductor body, in order to form sourcedrain regions;
etching trenches arranged parallel at a distance from one another into the semiconductor body;
forming bit lines running parallel to the trenches and arranged between adjacent ones of said trenches on the top side of the semiconductor body, each bit line being electrically conductively connected to sourcedrain regions located between the adjacent ones of the trenches;
forming supporting structures outside a memory cell array region, the supporting structures being formed concurrently with the bit lines;
applying a covering layer on the top side of the semiconductor body;
applying a storage layer to the walls of the trenches;
filling the trenches with conductive gate electrode material;
after filling the trenches, grinding back the top side in a planarizing manner until a top side of the covering layer is reached, wherein the supporting structures serve to support the planarizing outside the memory cell array region;
after the grinding back, depositing conductive word line material; and
patterning the conductive word line material to form word lines that run transversely with respect to the direction of the bit lines, the word lines being electrically conductively coupled to gate electrode disposed within the trenches.
2. The method as claimed in claim 1, wherein the grinding back is performed by means of chemical mechanical polish (CMP).
3. The method as claimed in claim 2, wherein applying a covering layer comprising forming a nitride or oxide layer over the bit lines.
4. The method as claimed in claim 3, wherein the covering layer is used as a stop layer during the grinding back of the conductive gate electrode material.
5. The method as claimed in claim 4 wherein the conductive gate electrode material comprises polysilicon.
6. The method as claimed in claim 1, wherein applying a covering layer comprising forming a nitride or oxide layer over the bit lines.
7. The method as claimed in claim 6, wherein the covering layer is used as a stop layer during the grinding back of the conductive gate electrode material.
8. The method as claimed in claim 7, wherein the conductive gate electrode material comprises polysilicon.
9. The method as claimed in claim 1, wherein the conductive gate electrode material comprises polysilicon.
10. The method as claimed in claim 9, wherein the conductive word line material comprises polysilicon.
11. A method for fabricating a memory cell, the method comprising:
patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material;
forming a doped region for a source and a doped region for a drain;
forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench;
applying a boundary layer, a memory layer and a boundary layer on top of one another over an entire surface of the semiconductor material;
introducing an electrically conductive material for a gate electrode into the trench;
planarizing an upper surface of the electrically conductive material; and
forming electrically conductive word lines over the planarized upper surface.
12. The method of claim 11 wherein the semiconductor material comprises a semiconductor layer.
13. The method of claim 11 wherein forming a doped region for a source and a doped region for a drain comprises performing an implantation.
14. The method of claim 11 wherein forming a doped region for a source and a doped region for a drain comprises diffusing dopant out of a material of the electrically conductive layer.
15. The method of claim 11 and further comprising forming support structures in a region spaced from any memory cells, wherein the planarizing step planarizes the upper surface to a level related to the height of the support structures.
16. The method of claim 11, wherein the electrically conductive material comprises polysilicon.
17. The method of claim 16, wherein forming word lines comprises depositing and patterning polysilicon.
18. The method of claim 11 wherein the planarizing step comprises performing a chemical mechanical polish (CMP).
19. The method of claim 11 and further comprising forming a covering layer over the electrically conductive film, the covering layer being formed into strip-like sections along with the electrically conductive film.
20. The method of claim 19 wherein the covering layer is used as a mask during the forming of a trench.