1461188736-38a86227-6c13-463e-8123-08dd71bfc714

1. A method comprising:
receiving, at a pulse width modulation (PWM) signal generator, an input PWM signal; and
generating, at the PWM signal generator and based on the input PWM signal, multiple output PWM signals that have duty ratios substantially equal to a duty ratio of the input PWM signal and that are synchronized to a synchronization signal and that have predetermined phase-shifts in relation to each other, and such that a PWM cycle of a leading output PWM signal of the multiple output PWM signals is prematurely terminated in response to a synchronization event represented by the synchronization signal so as to result in a prematurely-terminated PWM cycle for the leading output PWM signal and such that the prematurely-terminated PWM cycle is replicated for each non-leading PWM signal of the multiple output PWM signals while maintaining the predetermined phase-shifts between the multiple output PWM signals.
2. The method of claim 1, further comprising:
controlling a plurality of light emitting diode (LED) strings using the multiple output PWM signals.
3. The method of claim 1, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
4. The method of claim 1, wherein the PWM cycle comprises a first PWM cycle and generating the multiple output PWM signals comprises:
initiating generation of the first PWM cycle for a first set of intermediate PWM signals at a first signal generation unit of the PWM signal generator, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
prematurely terminating generation of the first PWM cycle for a leading intermediate PWM signal of the first set in response to the synchronization event;
replicating a completed portion of the first PWM cycle for the leading intermediate PWM signal for the first PWM cycle of each non-leading intermediate PWM signal of the first set;
generating a second PWM cycle for a second set of intermediate PWM signals at a second signal generation unit of the PWM signal generator in response to the synchronization event, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and
combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set to generate the multiple output PWM signals.
5. The method of claim 4, further comprising:
generating a third PWM cycle for a third set of intermediate PWM signals at a third signal generation unit of the PWM signal generator in response to a completion of the second PWM cycle; and
wherein combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set comprises combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set and a corresponding intermediate PWM signal of the third set to generate the multiple output PWM signals.
6. The method of claim 4, further comprising:
sampling, at the PWM signal generator, a first PWM cycle of the input PWM signal to determine a first value representative of a duty ratio of the first PWM cycle of the input PWM signal;
sampling, at the PWM signal generator, a second PWM cycle of the input PWM signal following the first PWM cycle of the input PWM signal to determine a second value representative of a duty ratio of the second PWM cycle of the input PWM signal;
wherein initiating generation of the first PWM cycle for the first set of intermediate PWM signals comprises timing generation of active segments of the first PWM cycle for each intermediate PWM signal of the first set based on the first value; and
wherein generating the second PWM cycle for the second set of intermediate PWM signals comprises timing generation of active segments of the second PWM cycle for each intermediate PWM signal of the second set based on the second value.
7. The method of claim 1, further comprising:
sampling, at the PWM signal generator, a PWM cycle of the input PWM signal to determine a value representative of a duty ratio of the PWM cycle; and
wherein generating the multiple output PWM signals comprises timing the multiple output PWM signals based on the value.
8. In a pulse width modulation (PWM) signal generator receiving an input PWM signal and outputting a plurality of output PWM signals synchronized to a synchronization signal, each output PWM signal phase-shifted in relation to the other output PWM signals, a method comprising:
initiating generation of a first PWM cycle for a leading output PWM signal of the plurality of output PWM signals at a first time;
prematurely terminating generation of the first PWM cycle for the leading output PWM signal in response to a synchronization event represented by the synchronization signal at a second time following the first time;
replicating that portion of the first PWM cycle for the leading output PWM signal generated prior to the second time for a first PWM cycle of each non-leading output PWM signal of the plurality of output PWM signals, the first PWM cycle of each non-leading output PWM signal corresponding to the first PWM cycle of the leading output PWM signal;
generating a second PWM cycle for the leading output PWM signal in response to the synchronization event; and
generating a second PWM cycle for each non-leading output PWM signal in response to the synchronization event, the second PWM cycle of each non-leading output PWM signal corresponding to the second PWM cycle of the leading output PWM signal.
9. The method of claim 8, further comprising:
controlling a plurality of light emitting diode (LED) strings using the plurality of output PWM signals.
10. The method of claim 8, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
11. A system comprising:
a pulse width modulation (PWM) signal generator comprising an input to receive an input PWM signal and outputs to provide multiple output PWM signals, the PWM signal generator to generate the multiple output PWM signals having substantially equal duty ratios and that are synchronized to a synchronization signal and having predetermined phase-shifts in relation to each other, and such that a PWM cycle of a leading output PWM signal of the multiple output PWM signals is prematurely terminated in response to a synchronization event represented by the synchronization signal so as to result in a prematurely-terminated PWM cycle for the leading output PWM signal and such that the prematurely-terminated PWM cycle is replicated for each of the non-leading output PWM signals of the multiple output PWM signals while maintaining the predetermined phase-shifts between the multiple output PWM signals.
12. The system of claim 11, further comprising:
a display comprising a plurality of light emitting diode (LED) strings and a plurality of current regulators, each current regulator to regulate a current through a corresponding LED string using a corresponding output PWM signal of the multiple output PWM signals.
13. The system of claim 11, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
14. The system of claim 11, wherein the PWM cycle comprises a first PWM cycle and wherein the PWM signal generator is to generate the multiple output PWM signals by: initiating generation of the first PWM cycle for a first set of intermediate PWM signals at a first signal generation unit of the PWM signal generator, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; prematurely terminating generation of the first PWM cycle for a leading intermediate PWM signal of the first set in response to the synchronization event; replicating a completed portion of the first PWM cycle for the leading intermediate PWM signal for the first PWM cycle of each non-leading intermediate PWM signal of the first set; generating a second PWM cycle for a second set of intermediate PWM signals at a second signal generation unit of the PWM signal generator in response to the synchronization event, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set to generate the multiple output PWM signals.
15. The system of claim 14, wherein the PWM signal generator further is to generate a third PWM cycle for a third set of intermediate PWM signals at a third signal generation unit of the PWM signal generator in response to a completion of the second PWM cycle, and wherein the PWM signal generator is to combine each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set and a corresponding intermediate PWM signal of the third set to generate the multiple output PWM signals.
16. The system of claim 14, wherein:
the PWM signal generator comprises a sampling module, the sampling module to sample a first PWM cycle of the input PWM signal to determine a first value representative of a duty ratio of the first PWM cycle of the input PWM signal and sample a second PWM cycle of the input PWM signal following the first PWM cycle of the input PWM signal to determine a second value representative of a duty ratio of the second PWM cycle of the input PWM signal; and
the PWM signal generator is to initiate generation of the first PWM cycle for the first set of intermediate PWM signals by timing generation of active segments of the first PWM cycle for each intermediate PWM signal of the first set based on the first value, and the PWM signal generator is to generate the second PWM cycle for the second set of intermediate PWM signals by timing generation of active segments of the second PWM cycle for each intermediate PWM signal of the second set based on the second value.
17. The system of claim 11, wherein:
the PWM signal generator further comprises a sampling module to sample a PWM cycle of the input PWM signal to determine a value representative of a duty ratio of the PWM cycle; and
the PWM signal generator is to generate the multiple output PWM signals by timing the multiple output PWM signals based on the value.
18. The system of claim 11, wherein the PWM signal generator comprises:
a first signal generation unit to generate a first set of intermediate PWM signals based on a first count value of a first counter, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
a second signal generation unit to generate a second set of intermediate PWM signals based on a second count value of a second counter, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
a third signal generation unit to generate a third set of intermediate PWM signals based on a third count value of a third counter, the third set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and
a signal combination module to combine the first set of intermediate PWM signals, the second set of intermediate PWM signals, and the third set of intermediate PWM signals to generate the multiple output PWM signals.
19. The system of claim 18, wherein:
the first signal generation unit is to initiate generation of a PWM cycle for the first set of intermediate PWM signals responsive to an assertion of a first signal and the first signal generation unit is to assert a second signal responsive to completing generation of the PWM cycle for the first set;
the second signal generation unit is to initiate generation of a PWM cycle for the second set of intermediate PWM signals responsive to the assertion of the second signal and the second signal generation unit is to assert a third signal responsive to completing generation of the PWM cycle for the second set; and
the third signal generation unit is to initiate generation of a PWM cycle for the third set of intermediate PWM signals responsive to the assertion of the third signal and the third signal generation unit is to assert the first signal responsive to completing generation of the PWM cycle for the third set.
20. The system of claim 18, wherein the signal combination module comprises:
a first OR gate having a first input to receive a first intermediate PWM signal of the first set, a second input to receive a first intermediate PWM signal of the second set, and a third input to receive a first intermediate PWM signal of the third set, and an output to provide a first output PWM signal of the multiple output PWM signals; and
a second OR gate having a first input to receive a second intermediate PWM signal of the first set, a second input to receive a second intermediate PWM signal of the second set, and a third input to receive a second intermediate PWM signal of the third set, and an output to provide a second output PWM signal of the multiple output PWM signals.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data processing apparatus switchable between a power saving mode and a normal operating mode, comprising:
a transition triggering event determining section for determining a transition triggering event that causes the data processing apparatus to shift from the power saving mode to the normal operating mode;
a transition triggering event holding section for storing the transition triggering event determined by the transition triggering event determining section;
a mode switching section for causing the data processing apparatus to switch between the power saving mode and the normal operating mode in accordance with the determination by the transition triggering event determining section;
an execution priority determining section for determining, based on the transition triggering event, an execution priority level andor an order of precedence in which a plurality of programs are executed during the normal operating mode; and
a program controlling section for executing the plurality of programs in accordance with the determination by the priority determining section.
2. The data processing apparatus according to claim 1 further comprising:
a document reader;
a document detector for detecting a document that should be read by the document reader;
wherein the transition triggering event is detection of the document by the document detector.
3. The data processing apparatus according to claim 2, wherein the priority determining section sets execution priority levels of programs executed when the document reader reads the document so that the execution priority levels are higher andor the order in which the programs are executed is increased.
4. The data processing apparatus according to claim 1 further comprising an authenticating section for authenticating a user of the data processing apparatus;
wherein the transition triggering event is authentication of the user.
5. The data processing apparatus according to claim 4, wherein the priority determining section sets, based on authentication by the authenticating section, execution priority levels of programs that the user is permitted to use so that the execution priority levels are higher andor the order in which the programs are executed is increased.
6. The data processing apparatus according to claims 1 further comprising a main controller to which a first power supply is supplied only when the data processing apparatus is in the normal operating mode, and a sub controller (200) to which a second power supply is supplied when the data processing apparatus is in the normal operating mode and when the data processing apparatus is in the power saving mode.
7. The data processing apparatus according to claims 1, wherein when the plurality of programs are executed concurrently, a time for which each one of the plurality of programs is executed increases with increasing a value of the execution priority level.
8. An image processing apparatus switchable between a power saving mode and a normal operating mode, comprising:
a transition triggering event determining section for determining a transition triggering event that causes the image processing apparatus to shift from the power saving mode to the normal operating mode;
a transition triggering event holding section for storing the transition triggering event determined by the transition triggering event determining section;
a mode switching section for causing the image processing apparatus to shift from the power saving mode to the normal operating mode in accordance with the determination by the transition triggering event determining section;
an execution priority determining section for determining, based on the transition triggering event, an execution priority level andor an order of precedence in which a plurality of programs are executed during the normal operating mode; and
a program controlling section for executing the plurality of programs in accordance with the determination by the priority determining section.
9. The image processing apparatus according to claim 8 further comprising:
a document reader);
a document detector for detecting a document that should be read by the document reader;
wherein the transition triggering event is detection of the document by the document detector.
10. The image processing apparatus according to claim 9, wherein the priority determining section sets execution priority levels of programs executed when the document reader reads the document so that the execution priority levels are higher andor the order in which the programs are executed is increased.
11. The image processing apparatus according to claim 8 further comprising an authenticating section for authenticating a user of the image processing apparatus;
wherein the transition triggering event is authentication of the user.
12. The image processing apparatus according to claim 11, wherein the priority determining section sets, based on authentication by the authenticating section, execution priority levels of programs that the user is permitted to use so that the execution priority levels are higher andor the order in which the programs are executed is increased.
13. A method for processing data, comprising:
determining a transition triggering event upon which a data processing apparatus shifts from a power saving mode to a normal operating mode, and then holding the transition triggering event;
shifting the data processing apparatus from the power saving mode to the normal operating mode in accordance with the transition triggering event;
determining execution priority levels of a plurality of programs executed when the data processing apparatus is in the normal operating mode andor an order of precedence in which the plurality of programs are executed; and
performing execution of the plurality of programs in accordance with the execution priority levels.
14. The method according to claim 13, wherein the transition triggering event is detection of a document placed on a document reader.
15. The method according to claim 14, wherein the determining is performed such that programs involved in reading the document are given higher execution priority levels andor or higher order of precedence.
16. The method according to claim 13, wherein the transition triggering event is a request for user authentication.
17. The method according to claim 16, wherein the determining is performed such that programs involved in reading the document are given higher execution priority levels andor or higher order of precedence.
18. The method according to claim 13, further comprising supplying electric power to a main controller only when the data processing apparatus is in the normal operating mode and to a sub controller when the data processing apparatus is in the power saving mode and in the normal operating mode.
19. The method according to claim 13, wherein programs having higher execution priority levels are executed longer time when the plurality of programs are concurrently executed.