1. A semiconductor memory device comprising:
a memory cell array which includes a plurality of subarrays arranged in the form of a matrix, and a plurality of word lines and a plurality of bit lines connected to the subarrays, the subarray comprising a bit line driving transistor which drives the bit line, a sub-bit line connected to the gate of the bit line driving transistor, and a plurality of memory cell transistors which are connected to the sub-bit line and drive the sub-bit line according to signals from the word lines, wherein:
the bit line driving transistor has a drain connected to the bit line and a source connected to a first power potential supply line; and
the subarray further includes a transmission transistor, which has a gate connected to the bit line and a drain connected to the sub-bit line, and a loading transistor section which includes a loading transistor or a series circuit comprised of plural loading transistors whose gates are connected each other, and
the loading transistor section, which has the series circuit, having a configuration where the gates is connected to the second power potential supply line, the outermost source is connected to the first power potential supply line, and the outermost drain is connected to the source of the transmission transistor.
2. The semiconductor memory device according to claim 1, wherein the single loading transistor section is provided to the subarrays as one common loading transistor section by connecting the common loading transistor section to the sources of the transmission transistors of the subarrays.
3. The semiconductor memory device according to claim 1, wherein the memory cell transistors are each provided in such a way that the gate is connected to the word line, the source is connected to a second power potential supply line, and the connection of the drain to the sub-bit line depends on data to be stored.
4. The semiconductor memory device according to claim 1, wherein the memory cell transistors are each provided in such a way that the gate is connected to the word lines, the source is connected to the second power potential supply line, the drain is connected to the sub-bit line, and the threshold value varies in correspondence to stored data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A ZnO film comprising ZnO doped with (a) a Group I or Group III element and (b) a Group VII element when doped with a Group I element or a Group V element when doped with a Group III element
2. A ZnO film according to claim 1, wherein the content of the (a) element is in the range of about 1% to 16% by weight and the content of the (b) element is in the range of about 0.5% to 8% by weight.
3. A ZnO film according to claim 1, wherein the ZnO is doped with a Group V element and a Group III element.
4. A ZnO film according to claim 3, wherein the Group III element is selected from the group consisting of Sc, Y, La, Ac, B, Al, Ga, In, Tl, lanthanides and actinides, and the Group V element is selected from the group consisting of N, V, Nb, Ta, P, As, Sb and Bi
5. A ZnO film according to claim 4, wherein the content of the Group III element is in the range of about 0.5% to 8% by weight and the content of the Group V element is in the range of about 1% to 16% by weight.
6. A ZnO film according to claim 5, wherein the content of the Group V element is higher than the content of the Group III element.
7. A ZnO film according to claim 6, wherein the Group V element is Y or Ga and the Group III element is N, Bi or As.
8. A ZnO film according to claim 3, wherein the content of the Group V element is higher than the content of the Group III element.
9. A ZnO film according to claim 1, wherein the ZnO is doped with a Group I element and a Group VII element.
10. A ZnO film according to claim 9, wherein the content of the Group I element is more higher than the content of the Group VII element.
11. A ZnO film according to claim 10, wherein the Group I element is Cu and the Group VII element is Mn.
12. A method for manufacturing a ZnO film, comprising:
providing a target comprising Zn metal or ZnO ceramic doped with a Group I element or Group III element; and depositing a ZnO film on a substrate from the target,
wherein before or after said depositing, a Group VII element is doped to the Group I doped Zn-containing material or a Group V element is doped to the Group III doped Zn-containing material.
13. A method for manufacturing a ZnO film according to claim 12, wherein the ZnO film is deposited on the substrate by a method selected from the group consisting of sputtering, electron cyclotron resonance (ECR) sputtering, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).
14. A method for manufacturing a ZnO film according to claim 12, wherein the target is doped with the Group III element.
15. A method for manufacturing a ZnO film according to claim 14, wherein the target is doped with the Group V element by implantation after said depositing.
16. A method for manufacturing a ZnO film according to claim 14, wherein the target is doped with the Group V element before said depositing.
17. A method for manufacturing a ZnO film according to claim 14, wherein the target is doped with the Group I element.
18. A luminescent element comprising p-type layer in which the p-type layer comprises a ZnO film according to claim 1.
19. A luminescent element comprising p-type layer in which the p-type layer comprises a ZnO film according to claim 3.
20. A luminescent element comprising p-type layer in which the p-type layer comprises a ZnO film according to claim 9.