1. A first wireless device comprising:
a wireless local area network (WLAN) module configured to selectively operate in a power save mode, wherein while not operating in the power save mode, the WLAN module is configured to communicate with a second wireless device;
a mobile phone radio module configured to receive, in accordance with a mobile phone protocol, base station time reference information from a base station;
a time module configured to maintain, at least while the WLAN module is operating in the power save mode, a base station time reference based on the base station time reference information received in accordance with the mobile phone protocol; and
a sleep module configured to control, based on the base station time reference maintained by the time module, when the WLAN module exits the power save mode to permit the WLAN module to communicate with the second wireless device.
2. The first wireless device of claim 1, further comprising an association module configured to receive and store settings common to a group including the first wireless device and the second wireless device.
3. The first wireless device of claim 2, wherein the association module is configured to request participation of the first wireless device in the group.
4. The first wireless device of claim 3, wherein the association module is configured to communicate with a coordination manager to request participation of the first wireless device in the group.
5. The first wireless device of claim 4, wherein the coordination manager specifies the base station from which the mobile phone radio module is to receive the base station time reference information.
6. The first wireless device of claim 4, wherein the coordination manager specifies a wireless channel for the WLAN module to use in communicating with the second wireless device.
7. The first wireless device of claim 4, wherein the coordination manager specifies an offset between the base station time reference information and base station time reference information from an alternative base station.
8. The first wireless device of claim 4, wherein the association module is configured to communicate with the coordination manager via the WLAN module.
9. The first wireless device of claim 1, wherein the sleep module is configured to (i) monitor, using the base station time reference, a length of time the WLAN module is in the power save mode, and (ii) control the WLAN module to exit the power save mode in response to the length of time reaching a predetermined value.
10. The first wireless device of claim 9, wherein the predetermined value is determined in agreement with the second wireless device.
11. A method of operating a first wireless device, the method comprising:
selectively operating a wireless local area network (WLAN) module of the first wireless device in a power save mode;
while not operating the WLAN module in the power save mode, communicating wirelessly with a second wireless device using the WLAN module;
receiving, in accordance with a mobile phone protocol, base station time reference information from a base station;
maintaining, at least while operating the WLAN module in the power save mode, a base station time reference based on the base station time reference information received in accordance with the mobile phone protocol; and
controlling, based on the maintained base station time reference, when the WLAN module exits the power save mode to permit the WLAN module to communicate with the second wireless device.
12. The method of claim 11, further comprising receiving and storing settings common to a group including the first wireless device and the second wireless device.
13. The method of claim 12, further comprising requesting participation of the first wireless device in the group.
14. The method of claim 13, further comprising communicating with a coordination manager to request participation of the first wireless device in the group.
15. The method of claim 14, further comprising, in response to the coordination manager, determining the base station from which to receive the base station time reference information.
16. The method of claim 14, further comprising, in response to the coordination manager, determining a wireless channel to use in communicating with the second wireless device.
17. The method of claim 14, further comprising, in response to the coordination manager, determining an offset between the base station time reference information and base station time reference information from an alternative base station.
18. The method of claim 14, further comprising communicating with the coordination manager via the WLAN module.
19. The method of claim 11, further comprising:
monitoring, using the base station time reference, a length of time the WLAN module is in the power save mode; and
controlling the WLAN module to exit the power save mode in response to the length of time reaching a predetermined value.
20. The method of claim 19, further comprising determining the predetermined value in agreement with the second wireless device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A test circuit formed on a surface of a semiconductor wafer having a plurality of chip areas for placing semiconductor product chips and scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested;
a selection circuit that sequentially selects at least one of the elements at a time; and
a plurality of pads used for testing the elements,
wherein the test circuit and the pads are placed within one of the scribe lines.
2. The test circuit according to claim 1, wherein a number of the elements included in the test circuit is at least 100.
3. The test circuit according to claim 1, wherein:
the plurality of pads comprise at least one input pad to input an input signal to the selected one of the elements and at least one output pad to output an output signal from the selected one of the elements.
4. The test circuit according to claim 3, wherein the test circuit further comprises:
at least one switch to supply the input signal from the input pad to the selected one of the elements or to supply the output signal of the selected one of the elements to the output pad.
5. The test circuit according to claim 3, wherein the plurality of pads further comprises at least one power supply pad to supply an electric power to the selection circuit and at least one control pad to supply a control signal to the selection circuit.
6. The test circuit according to claim 1, wherein:
the plurality of pads comprise at least three pads arranged along a longitudinal direction of one of the scribe lines; and
the plurality of elements are divided into at least two groups, each including at least two elements, at least two of the groups of elements are separately arranged in respective spaces between adjacent ones of the at least three pads.
7. The test circuit according to claim 6, wherein:
the selection circuit comprises a shift register having a plurality of shift stages, each for selecting at least one of the elements; and
the shift stages of the shift register that select the elements included in at least two of the groups are arranged together with corresponding elements in the respective spaces.
8. A test circuit formed on a surface of a semiconductor wafer having a plurality of chip areas for placing semiconductor product chips and scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested; and
a shift register comprising a plurality of shift stages, each for selecting a predetermined number of the elements, wherein:
each of the shift stages of the shift register and the predetermined number of the elements that can be selected by each of the shift stages are arranged along a direction generally perpendicular to a longitudinal direction of one of the scribe lines to form a unit having a dimension that can be placed within one of the scribe lines; and
the test circuit includes at least one block, each comprising a plurality of the units arranged along the longitudinal direction of one of the scribe lines.
9. The test circuit according to claim 8, wherein a number of the elements included in the test circuit is at least 100.
10. The test circuit according to claim 8, wherein:
the test circuit further comprises at least three pads used for testing the elements and arranged along the longitudinal direction of one of the scribe lines; and
the at least one block comprises at least two blocks separately arranged in respective spaces between adjacent ones of the at least three pads.
11. A semiconductor product wafer comprising:
a plurality of product chips placed within respective chip areas arranged on a surface of the semiconductor product wafer and a test circuit, the test circuit comprising:
a plurality of elements to be tested;
a selection circuit that sequentially selects at least one of the elements at a time; and
a plurality of pads used for testing the elements,
wherein the test circuit and the pads are placed within one of scribe lines that separate the chip areas.
12. The semiconductor product wafer according to claim 11, wherein a number of the elements included in the test circuit is at least 100.
13. The semiconductor product wafer according to claim 11, wherein:
the plurality of pads comprise at least three pads arranged along a longitudinal direction of one of the scribe lines; and
the plurality of elements are divided into at least two groups, each comprising at least two of the elements,
wherein at least two of the groups of elements are separately arranged in respective spaces between adjacent ones of the at least three pads.
14. The semiconductor product wafer according to claim 13, wherein:
the selection circuit comprises a shift register comprising a plurality of shift stages, each for selecting at least one of the elements; and
the shift stages of the shift register that select the elements included in at least two of the groups are arranged together with the corresponding elements in the respective spaces.
15. A semiconductor product wafer comprising:
a plurality of product chips placed within respective chip areas arranged on a surface of the semiconductor product wafer and a test circuit placed within one of scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested; and
a shift register comprising a plurality of shift stages, each for selecting a predetermined number of the elements, wherein:
each of the shift stages of the shift register and the predetermined number of the elements that can be selected by the each of the shift stages are arranged along a direction generally perpendicular to a longitudinal direction of one of the scribe lines to form a unit having a dimension that can be placed within one of the scribe lines; and
the test circuit comprises at least one block, each comprising a plurality of the units arranged along the longitudinal direction of one of the scribe lines.
16. The semiconductor product wafer according to claim 15, wherein a number of the elements included in the test circuit is at least 100.
17. The semiconductor product wafer according to claim 15, wherein:
the test circuit further comprises at least three pads used for testing the elements and arranged along the longitudinal direction of one of the scribe lines; and
the at least one block comprises at least two blocks separately arranged in respective spaces between adjacent ones of the at least three pads.
18. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers by the manufacturing process, each of the product wafers comprising:
a plurality semiconductor product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and
a test circuit placed within one of scribe lines between the chip areas, the test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time;
testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers; and
evaluating results of the testing to monitor the manufacturing process.
19. The method according to claim 18, wherein a number of the elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before a decrease of a yield of the semiconductor product chips occurs.
20. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers including different types of semiconductor product wafers at an arbitrary ratio in an arbitrary order by the manufacturing process, each of the different types of semiconductor product wafers comprising:
a plurality of one of different types of product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and
a common test circuit placed within one of scribe lines between the chip areas, the common test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time;
selecting a plurality of the manufactured semiconductor product wafers comprising at least two of the different types of the semiconductor product wafers;
testing each of the elements in the test circuit in the selected semiconductor product wafers; and
evaluating results of the testing to monitor the manufacturing process.
21. The method according to claim 20, wherein a number of elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before a decrease in a yield of the different types of product chips occurs.
22. The method according to claim 20, wherein the evaluating step is performed when a decrease in a yield of at least one of the different types of product chips occurs.
23. The method according to claim 20, further comprising:
adjusting the manufacturing process according to a result of the evaluating to prevent occurrence of a decrease in a yield of at least one of the different types of product chips.
24. The method according to claim 20, wherein the plurality of manufactured semiconductor product wafers are selected such that the selected semiconductor product wafers are manufactured with approximately a fixed interval.
25. The method according to claim 20, wherein different customers provide mask patterns used to manufacture the different types of product chips.
26. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers, each including a plurality of product chips and a test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the plurality of elements at a time;
testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers;
evaluating results of the testing; and
adjusting the manufacturing process according to the results of the evaluating to prevent occurrence of a decrease in a yield of the product chips.
27. The method according to claim 26, wherein a number of the elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before the decrease in the yield of the product chips occurs.