1. An organic electroluminescence device comprising:
a substrate;
a first colored layer disposed above a first surface of the substrate;
a first luminescence element which is disposed between the first surface of the substrate and the first colored layer, and has a stack structure where a first pixel electrode, a functional layer including a luminescence layer, and an opposite electrode are stacked;
a first reflection layer which is disposed between the first surface and the first pixel electrode, and forms a first resonator structure between the first reflection layer and the opposite electrode; and
an insulation layer disposed between the first surface and the functional layer through the first pixel electrode,
wherein the first pixel electrode includes a first portion which does not overlap the insulation layer and a second portion which overlaps the insulation layer in a plan view,
wherein light emitted from the first luminescence element includes a first light, which is emitted from a portion which overlaps the first portion of the functional layer and has a first peak wavelength, and a second light, which is emitted from a portion which overlaps the second portion of the functional layer and has a second peak wavelength, and
wherein a film thickness of the insulation layer or optical characteristics of the first colored layer are set so that the first light is transmitted through the first colored layer more than the second light is.
2. The organic electroluminescence device according to claim 1,
wherein transmittance of the second light in the first colored layer is equal to or less than 15%.
3. The organic electroluminescence device according to claim 1,
wherein the film thickness of the isolation layer is set so that transmittance of the second light in the first colored layer is equal to or less than 15%.
4. The organic electroluminescence device according to claim 1, further comprising:
a second colored layer which has different transmission characteristics of light from the first colored layer;
a second luminescence element which is disposed between the first surface and the second colored layer, and has a stack structure in which a second pixel electrode, the functional layer, and the opposite electrode are stacked; and
a second reflection layer which is disposed between the first surface and the second pixel electrode, and forms a second resonator structure between the second reflection layer and the opposite electrode,
wherein the second pixel electrode includes a third portion which does not overlap the insulation layer and a fourth portion which overlaps the insulation layer,
wherein light emitted from the second luminescence element includes a third light, which is emitted from a portion overlapping the third portion of the functional layer and has a third peak wavelength, and a fourth light which is emitted from a portion overlapping the fourth portion of the functional layer and has a fourth peak wavelength,
wherein the second colored layer absorbs the fourth light more than the third light, and
wherein the film thickness of the insulation layer overlapping the second portion is different from the film thickness of the insulation layer overlapping the fourth portion.
5. The organic electroluminescence device according to claim 1, further comprising:
a third colored layer which has different transmission characteristics of light from the first colored layer;
a third luminescence element which is disposed between the first surface and the third colored layer and has a stack structure in which a third pixel electrode, the functional layer, and the opposite electrode are stacked; and
a third reflection layer which is disposed between the first surface and the third pixel electrode and forms a third resonator structure between the third reflection layer and the opposite electrode,
wherein the third pixel electrode includes a fifth portion which does not overlap the insulation layer and a sixth portion which overlaps the insulation layer,
wherein light released from the third luminescence element includes a fifth light, which is emitted from a portion overlapping the fifth portion of the functional layer and has a fifth peak wavelength, and a sixth light, which is emitted from a portion overlapping the sixth portion of the functional layer and has a sixth peak wavelength, and
wherein the third colored layer transmits 15% or more of the fifth light and the sixth light.
6. An organic electroluminescence device comprising:
a substrate;
a first colored layer which is disposed on a first surface of the substrate;
a first luminescence element which is disposed between the first surface of the substrate and the first colored layer, and has a stack structure in which a first pixel electrode, a functional layer including a luminescence layer, and an opposite electrode are stacked,
a first reflection layer which is disposed between the first surface and the first pixel electrode, and forms a first resonator structure between the first reflection layer and the opposite electrode; and
an insulation layer which is disposed between the first surface and the functional layer through the first pixel electrode,
wherein the first pixel electrode includes a first portion which does not overlap the insulation layer, and a second portion which overlaps the insulation layer in a plan view,
wherein light released from the first luminescence element includes a first light, which is emitted from a portion overlapping the first portion of the functional layer and has a first peak wavelength, and a second light, which is emitted from a portion overlapping the second portion of the functional layer and has a second peak wavelength, and
wherein a film thickness of the insulation layer or optical characteristics of the first colored layer are set so that transmittance of light of the first colored layer in the first peak wavelength is higher than transmittance of light of the first colored layer in the second peak wavelength.
7. An electronic apparatus comprising the organic electroluminescence device according to claim 1.
8. An electronic apparatus comprising the organic electroluminescence device according to claim. 2.
9. An electronic apparatus comprising the organic electroluminescence device according to claim 3.
10. An electronic apparatus comprising the organic electroluminescence device according to claim 4.
11. An electronic apparatus comprising the organic electroluminescence device according to claim 5.
12. An electronic apparatus comprising the organic electroluminescence device according to claim 6.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for testing data from devices under test (DUTs), said method comprising:
strobing first data that is output from a first logic block through a multiplexer to a plurality of channels that are allocated between said first logic block and a second logic block wherein said second logic block is placed on hold during said strobing first data and wherein further said strobing first data is performed using a first programmable strobing edge number;
testing said first data against expected data and, responsive to a detected failure of said first data, reporting said failure and said first programmable strobing edge number within a first flag structure;
strobing second data that is output from said second logic block through said multiplexer to said plurality of channels allocated between said first logic block and said second logic block wherein said first logic block is placed on hold during said strobing second data and wherein further said strobing second data is performed using a second programmable strobing edge number; and
testing said second data against expected data and, responsive to a detected failure of said second data, reporting said failure and said second programmable strobing edge number within a second flag structure.
2. A method as described in claim 1 further comprising determining whether said first logic block andor said second logic block failed by examining strobing edge number information within said first and second flag structures, and wherein said first logic block is contained in a first DUT and said second logic is contained in a second DUT.
3. A method as described in claim 2 further comprising, during said strobing first data, configuring said multiplexer to only access parallel inputoutput (IO) pins from said first DUT and wherein said first programmable strobing edge number is reserved for said first DUT.
4. A method as described in claim 3 further comprising, during said strobing second data, configuring said multiplexer to only access parallel IO pins from said second DUT and wherein said second programmable strobing edge number is reserved for said second DUT.
5. A method as described in claim 4, wherein said first data is first parallel data of a scan test, wherein said second data is second parallel data of said scan test, and wherein said testing said first data further comprises testing said first data against expected data and, responsive to a detected failure of said first data at a respective channel, reporting said failure, said respective channel, and said first programmable strobing edge number within said first flag structure.
6. A method as described in claim 1, wherein said first logic block and said second logic block are contained within a same DUT, and wherein said DUT comprises said multiplexer.
7. A method as described in claim 2 wherein said plurality of channels allocated between said first DUT and to said second DUT are part of a tester system and wherein said tester system also comprises a plurality of channels dedicated to scanin and scanout testing of said first DUT and a plurality of channels dedicated to scanin and scanout testing of said second DUT.
8. A system for testing devices under test (DUTs), said system comprising:
a tester system comprising:
tester logic;
a first plurality of channels dedicated to testing of a first DUT;
a second plurality of channels dedicated to testing of a second DUT;
a third plurality of channels operable to be allocated between said first DUT and said DUT for parallel testing of said first DUT and said second DUT; and
a multiplexer operable to selectively couple inputoutput (IO) pins of a first DUT or IO pins of a second DUT to the tester system, wherein said multiplexer is coupled to said third plurality of channels of said tester system, wherein said third plurality of channels are allocated between said first DUT and said second DUT;
wherein said tester logic is operable to perform a test method, said test method comprising:
strobing first data that is output from said first DUT through said multiplexer to said third plurality of channels while second DUT is placed on hold and wherein said strobing first data is performed using a first programmable strobing edge number;
testing said first data against expected data and, responsive to a detected failure of said first data, reporting said failure and said first programmable strobing edge number within a first flag structure;
strobing second data that is output from said second DUT through said multiplexer to said third plurality of channels while said first DUT is placed on hold and wherein said strobing second data is performed using a second programmable strobing edge number; and
testing said second data against expected data and, responsive to a detected failure of said second data, reporting said failure and said second programmable strobing edge number within a second flag structure.
9. A system as described in claim 8 wherein said test method further comprises determining whether said first DUT andor said second DUT failed by examining strobing edge number information within said first and second flag structures.
10. A system as described in claim 8 wherein said test method further comprises, during said strobing first data, configuring said multiplexer to only access parallel inputoutput (IO) pins from said first DUT, wherein said multiplexer is disposed on a loadboard of said system.
11. A system as described in claim 10, wherein said first data and said second data are scan testing parallel data, and wherein said test method further comprises, during said strobing second data, configuring said multiplexer to only access parallel IO pins from said second DUT.
12. A system as described in claim 11 wherein said testing said first data further comprises testing said first data against expected data and, responsive to a detected failure of said first data at a respective channel, reporting said failure, said respective channel, and said first programmable strobing edge number within said first flag structure.
13. A system as described in claim 12 wherein said testing said second data further comprises testing said second data against expected data and, responsive to a detected failure of said second data at a respective channel, reporting said failure, said respective channel, and said second programmable strobing edge number within said second flag structure.
14. A system for testing devices under test (DUTs), said system comprising:
a tester system comprising:
memory;
tester logic;
strobing logic operable to strobe IO data from a first logic block or a second logic block according to a programmable strobing edge number;
a first plurality of channels dedicated to testing of said first logic block;
a second plurality of channels dedicated to testing of said second logic block;
a third plurality of channels operable to be allocated between said first logic block and said second logic block for parallel testing of said first logic block and said second logic block; and
a multiplexer operable to be selectively coupled to IO pins of a first logic block or IO pins of a second logic block and wherein said multiplexer is coupled to said third plurality of channels of said tester system, wherein said third plurality of channels are allocated between said first logic block and said second logic block during testing thereof,
and wherein said memory is configured for storing flag structures, a flag structure operable to indicate a failure associated with a channel of said third plurality of channels by recording a failure flag along with a strobing edge number coincident with said failure and wherein said strobing edge number indicates which logic block of said first and second logic block s failed.
15. A system as described in claim 14, wherein said first logic block is contained in a first DUT and said second logic block is contained in a second DUT, wherein said tester logic is operable to perform a test method, said test method comprising:
strobing first data that is output from said first DUT through said multiplexer to said third plurality of channels while second DUT is placed on hold and wherein said strobing first data is performed using said strobing logic configured for strobing using a first strobing edge number;
testing said first data against expected data and, responsive to a detected failure of said first data, reporting said failure and said first programmable strobing edge number within a first flag structure;
strobing second data that is output from said second DUT through said multiplexer to said third plurality of channels while said first DUT is placed on hold and wherein said strobing second data is performed using said strobing logic configured to strobe using a second programmable strobing edge number; and
testing said second data against expected data and, responsive to a detected failure of said second data, reporting said failure and said second programmable strobing edge number within a second flag structure.
16. A system as described in claim 15 wherein said test method further comprises determining whether said first DUT andor said second DUT failed by examining strobing edge number information of said first and second flag structures.
17. A system as described in claim 15 wherein said test method further comprises, during said strobing first data, configuring said multiplexer to only access parallel inputoutput (IO) pins from said first DUT.
18. A system as described in claim 17 wherein said test method further comprises, during said strobing second data, configuring said multiplexer to only access parallel IO pins from said second DUT, wherein said multiplexer is integrated in said first DUT and said second DUT.
19. A system as described in claim 15 wherein said testing said first data further comprises testing said first data against expected data and, responsive to a detected failure of said first data at a respective channel, reporting said failure, said respective channel, and said first programmable strobing edge number within said first flag structure.
20. A system as described in claim 15 wherein said first data and said second data are parallel data of scan testing.