1. A compound represented in the formula (I):
wherein, as valence and stability permit,
X is \u2014NH\u2014;
Z is a direct bond;
Y represents \u2014C(\u2550O);
A represents O, S, or NR7;
G represents cyclohexane, pyridine, phenyl or phenyl fused with 1,3-dioxolane;
Ar represents phenyl, pyridine, 1,3-thiazole or thiophene, optionally substituted by halogen, lower alkoxy, lower alkyl or halogenated lower alkyl;
R1 represents a disubstituted pyridine ring wherein the substitutents are selected from nitro, cyano, lower alkyl, halogenated lower alkyl, alkenyl, alkynyl, phenylalkyl, amino, alkylamino, acylamino, amido, hydroxyl, alkoxy, acyloxy, carbonyl, phosphoryl, sulfamoyl, sulfate, sulfonamide, sulfonate, sulfoxido, sulfhydryl, and sulfonyl;
R2 represents from 0-4 substituents on the ring to which it is attached wherein the substitutents are selected from halogen, lower alkyl, halogenated lower alkyl, lower alkenyl, 5, 6 or 7-membered single ring aryl, 5, 6 or 7-membered single ring heteroaryl with 1-4 heteroatoms, 3 to 7-membered heterocyclyl with 1-4 heteroatoms, ester, carboxyl, formyl, thioester, thiocarboxylate, thioformate, ketone, aldehyde, amino optionally substituted by alkyl, acylamino, amido, amidino, cyano, nitro, azido, alkylthio, sulfonyl, sulfoxido, sulfate, sulfonate, sulfamoyl, sulfonamido, phosphoryl, phosphonate, phosphinate, \u2014OH, \u2014SH, \u2014NH2, or any two R2, when occurring more than once in a cyclic or polycyclic structure, can be taken together form a 4- to 8-membered cycloalkyl, aryl, or heteroaryl;
R7, represents H, lower alkyl, or lower alkyl substituted by \u2014CONH2, morpholine, piperidine or piperidine N-substituted by \u2014COO-tert-butyl; and
J is absent.
2. The compound of claim 1, wherein R1 is pyridine disubstituted with a methyl and trifluoromethyl group.
3. The compound of claim 1, wherein R1 is 6-(trifluoromethyl)-2- methylpyridin -3-yl.
4. The compound of claim 1, wherein X and the ring comprising A are disposed on Ar in a meta relationship.
5. A pharmaceutical preparation comprising a sterile pharmaceutical excipient and a compound according to claim 1.
6. The compound of claim 1, which is of formula (II):
where G, A, X, Y, Z, J, R1 and R2 are as defined in claim 1 and R3 is halogen, lower alkoxy, lower alkyl or halogenated lower alkyl.
7. The compound of claim 6, wherein R3 is at a position on the ring para either to X or to the ring including A.
8. The compound of claim 7, wherein R3 is chloro.
9. The compound of claim 1, wherein Ar is substituted by chloro at a position on the ring para either to X or to the ring including A.
10. The compound of claim 1, wherein R2 represents from 0-4 substituents on the ring to which it is attached wherein the substitutents are selected from lower alkyl, halogenated lower alkyl, halogen, \u2014OH, acyl, acylamino, alkylthio, pyrrole, furazan and amine optionally substituted with alkyl.
11. The compound of claim 1, wherein R2 represents from 0-4 substituents on the ring to which it is attached wherein the substitutents are selected from: halogen; cyano; nitro; alkoxy; amino; acylamino; a substituted or unsubstituted cycloalkyl, 5, 6 or 7-membered single ring aryl, 5, 6 or 7-membered single ring heteroaryl with 1-4 heteroatoms, or 3 to 7-membered heterocyclyl with 1-4 heteroatoms fused to G; and substituted or unsubstituted lower alkyl.
12. The compound of claim 1, wherein the aryl and heteroaryl groups are selected from benzene, pyrrole, furan, thiophene, imidazole, oxazole, thiazole, triazole, pyrazole, pyridine, pyrazine, pyridazine and pyrimidine; and the heterocyclyl groups are selected from thiophene, thianthrene, furan, pyran, isobenzofuran, chromene, xanthene, phenoxathine, pyrrole, imidazole, pyrazole, isothiazole, isoxazole, pyridine, pyrazine, pyrimidine, pyridazine, indolizine, isoindole, indole, indazole, purine, quinolizine, isoquinoline, quinoline, phthalazine, naphthyridine, quinoxaline, quinazoline, cinnoline, pteridine, carbazole, carboline, phenanthridine, acridine, pyrimidine, phenanthroline, phenazine, phenarsazine, phenothiazine, furazan, phenoxazine, pyrrolidine, oxolane, thiolane, oxazole, piperidine, piperazine, morpholine, lactones, lactams, azetidinones, pyrrolidinones, sultams and sultones.
13. The compound of claim 1, which is selected from one of the following compounds 1- 38:
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A double-conversion tuner, comprising:
an input for receiving an RF signal having a number of channels;
a first mixer configured to up-convert said RF signal to a first IF signal using a first local oscillator signal;
a first local oscillator having a delta-sigma fractional-N phase lock loop to produce said first local oscillator signal, said delta-sigma fractional-N phase lock loop configured to perform fine tuning of said first local oscillator signal and configured to have a wide tuning range sufficient to cover said number of channels;
a bandpass filter configured to select a subset of channels from said first IF signal;
a second mixer configured to down-convert said subset of channels to a second IF signal using a second local oscillator signal; and
a second local oscillator configured to generate said second local oscillator signal, and configured to perform coarse frequency tuning and have a narrow tuning range relative to said first local oscillator.
2. The double-conversion tuner of claim 1, wherein said delta-sigma fractional-N phase lock loop includes:
a feedback path having a programmable frequency divider; and
a delta-sigma modulator configured to receive a static fractional input and generate an output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input, said output summed with an integer data value and arranged to control said programmable frequency divider.
3. The double-conversion tuner of claim 1, wherein said delta-sigma fractional-N phase lock loop includes:
a feedback path having a programmable frequency divider; and
a delta-sigma modulator configured to receive a static fractional input and generate an output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input, said output summed with a periodic bit stream including at least one of (0,1) and (0, 1) data values and arranged to control said programmable frequency divider.
4. The double-conversion tuner of claim 1, wherein said delta-sigma fractional-N phase lock loop includes:
a feedback path having a programmable frequency divider; and
a delta-sigma modulator configured to receive a static fractional input and generate an output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input, said output summed with an integer data value and with a periodic bit stream including at least one of (0,1) and (0, 1) data values and arranged to control said programmable frequency divider.
5. The double-conversion tuner of claim 2, wherein said output of said delta-sigma modulator is further summed with a periodic bit stream including at least one of (0,1) and (0, 1) data values.
6. The double-conversion tuner of claim 2, wherein said delta-sigma modulator includes:
a series of registers with a summer in-between adjacent registers;
a slicer configured to quantize an output of a last register in said series of registers so as to produce an integer at an output of said slicer; and
a plurality of multipliers configured to multiply said output of said slicer by a series of coefficients, outputs of said plurality of multipliers coupled to inputs of said summers that are in-between said adjacent registers.
7. The double-conversion tuner of claim 6, wherein said delta-sigma modulator further includes:
additional summers, each having one input coupled to an output of a corresponding multiplier of said plurality of multipliers and a second input coupled to an output of a corresponding register of said series of registers, an output of each of said additional summers coupled to said inputs of said summers that are in-between said adjacent registers.
8. The double-conversion tuner of claim 6, wherein said output of said slicer is one of 1, 0, and 1.
9. The double-conversion tuner of claim 2, wherein said delta-sigma modulator includes:
an input multiplier at an input to said delta-sigma modulator, said input multiplier configured to multiply said static fractional input by a coefficient;
a series of stages, each stage including:
a first summer;
a second summer;
a register; and
a stage multiplier, and
a slicer configured to quantize an output of a last register of a last stage of said series of stages so as to produce an integer at an output of said slicer,
wherein said stage multiplier is configured to multiply an output of said slicer by a coefficient, output of said stage multiplier coupled to an input of said first summer, output of said first summer coupled to an input of said second summer, output of said second summer coupled to an input of said register, output of said register coupled to said input of said first summer and an input of a subsequent stage, and output of said input multiplier coupled to an input of a first stage of said series of stages.
10. The double-conversion tuner of claim 2, wherein said delta-sigma modulator utilizes at least, three levels of quantization.
11. The double conversion tuner of claim 1, further comprising:
a second IF filter configured to select a desired channel from said subset of channels in said second IF signal.
12. The double-conversion tuner of claim 1, wherein said second local oscillator includes an integer-N phase lock loop.
13. The double-conversion tuner of claim 1, wherein said delta-sigma fractional-N phase lock loop includes a high-order loop filter to suppress modulation noise at high frequencies.
14. A method of receiving an RF signal, the method comprising the steps of:
(a) receiving an input RF signal having a number of channels;
(b) generating a first local oscillator signal;
(c) fine-tuning said first local oscillator signal;
(d) up-converting said input RF signal to a first IF signal using said first local oscillator signal;
(e) filtering said first IF signal to select a subset of channels from said first IF signal;
(f) generating a second local oscillator signal;
(g) coarsely-tuning said second local oscillator signal relative to said fine-tuning of step (c); and
(h) down-converting said subset of channels to a second IF signal using said second local oscillator signal.
15. The method of claim 14, wherein the fine-tuning step comprises:
(i) receiving a reference signal and a static fractional input;
(ii) modulating said reference signal with said static fractional input to generate an averaged output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input;
(iii) summing said averaged output with an integer data value;
(iv) dividing the frequency of said first local oscillator signal by said summed output of step (iii); and
(v) comparing said divided first local oscillator signal with said reference signal.
16. The method of claim 15, wherein said summing step (step (iii)) further comprises summing said averaged output with a periodic bit stream including at least one of (0,1) and (0, 1) data values.
17. The method of claim 15, wherein the modulating step comprises:
(i) Processing said reference signal and said static fractional input through a series of alternating summers and registers;
(ii) Quantizing the result of step (i) to produce said averaged output; and
(iii) Multiplying said averaged output by a plurality of coefficients.
18. The method of claim 17, further comprising summing said outputs of said multiplication with an output of a corresponding register of said alternating summers and registers prior to summing with an output of a preceding register.
19. The method of claim 17, wherein said averaged output is one of 1, 0, and 1.
20. The method of claim 15, wherein the modulation step uses at least three levels of quantization in order to obtain a fractional frequency intermediate between a highest and lowest integer frequency.
21. The method of claim 15, suppressing modulation noise generated during said modulation step.
22. The method of claim 14, wherein the fine-tuning step comprises:
(i) receiving a reference signal and a static fractional input;
(ii) modulating said reference signal with said static fractional input to generate an averaged output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input;
(iii) summing said averaged output with a periodic bit stream including at least one of (0,1) and (0, 1) data values;
(iv) dividing the frequency of said first local oscillator signal by said summed output of step (iii); and
(v) comparing said divided local oscillator signal with said reference signal.
23. The method of claim 14, wherein the fine-tuning step comprises:
(i) receiving a reference signal and a static fractional input;
(ii) modulating said reference signal with said static fractional input to generate an averaged output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input;
(iii) summing said averaged output with an integer data value and with a periodic bit stream including at least one of (0,1) and (0, 1) data values;
(iv) dividing the frequency of said first local oscillator signal by said summed output of step (iii); and
(v) comparing said divided local oscillator signal with said reference signal.
24. The method of claim 14, wherein the method further comprises filtering of said second IF signal to select a desired channel from said subset of channels in said second IF signal.
25. The method of claim 14, wherein said first local oscillator signal is generated by a delta-sigma fractional-N phase lock loop.
26. The method of claim 14, wherein said second local oscillator signal is generated by an integer-N phase lock loop.
27. A method of receiving an RF signal, the method comprising the steps of:
receiving an input RF signal having a number of channels;
up-converting said input RF signal to a first IF signal using a first local oscillator signal;
filtering said first IF signal to determine a selected channel from said first IF signal;
down-converting said selected channel to a second IF signal by adjusting said second local oscillator signal; and
fine tuning said selected channel by adjusting said first local oscillator signal, and coarse tuning said selected channel by adjusting said second local oscillator signal.
28. The method of claim 27, further comprising the steps:
generating said first local oscillator signal so as to reduce phase noise; and
generating said second local oscillator signal so as to reduce unwanted spurious signals.
29. The double conversion tuner of claim 1, wherein said delta-sigma fractional-N phase lock loop is configured to reduce phase noise of said double conversion tuner, and wherein said second local oscillator is configured to reduce unwanted spurious signals of said double conversion tuner.