1. A wiring board comprising:
an insulating board including a land conductor layer on a surface thereof;
an insulating layer formed on the insulating board;
a via hole reaching the land conductor layer from an upper surface of the insulating layer;
a via conductor formed in the via hole and formed of a plated metal layer; and
a wiring conductor formed on the via conductor and electrically connected to the via conductor,
wherein the via hole is provided with a protruding portion formed of copper foil and protruding from a periphery of an opening of the via hole toward a center of the opening.
2. The wiring board according to claim 1,
wherein the protruding portion protrudes from the periphery of the opening of the via hole toward the center of the opening by an amount of 3 to 15 \u03bcm.
3. The wiring board according to claim 1,
wherein the via conductor and the wiring conductor are formed integrally with the plated metal layer.
4. A method for manufacturing a wiring board, the method comprising the steps of:
sequentially laminating an insulating layer and copper foil on an insulating board including a land conductor layer on a surface thereof;
forming a via hole reaching the land conductor layer from an upper surface of the copper foil such that the via hole is provided with a protruding portion formed of the copper foil and protruding from a periphery of an opening of the via hole toward a center of the opening;
forming, on the copper foil, a plating resist layer including an opening portion for exposing the via hole and a periphery thereof;
forming a via conductor formed of a plated metal layer in the via hole and forming a wiring conductor in the opening portion of the plating resist layer; and
removing the plating resist layer and the copper foil in a portion covered with the plating resist layer.
5. The method for manufacturing a wiring board according to claim 4 further comprising a step of etching a surface of the copper foil after the step of forming the via hole.
6. The manufacturing method according to claim 4,
wherein the protruding portion protrudes from the periphery of the opening of the via hole toward the center of the opening by an amount of 3 to 15 \u03bcm.
7. The manufacturing method according to claim 4,
wherein the via conductor and the wiring conductor are formed integrally with the plated metal layer.
8. The manufacturing method according to claim 4,
wherein the copper foil is roughened.
9. The manufacturing method according to claim 4,
wherein the via hole provided with the protruding portion is formed by laser irradiation.
10. The manufacturing method according to claim 9, wherein
the laser irradiation is divided into two steps, and energy of laser irradiation in a second step is set weaker than that in a first step.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A timing control method for operating a synchronous memory, wherein the synchronous memory has a local data bus, a signal amplification bus, and a global data bus, the timing control method comprising the steps of:
providing a synchronous timing such that following operations are carried out in a (n+1)th clock cycle of the synchronous timing;
reading and decoding the (a+1)th address;
pre-charging the local data bus that stores the ath bath of local data into an initial value in a local data bus pre-charging period;
amplifying and transferring the ath batch of global data from the signal amplification bus to the global data bus in a global data transmission period;
transferring the (a+1)th batch of local data to the local data bus in a non-local data bus pre-charging period;
pre-charging the signal amplification bus and the global data bus that stores the ath batch of global data into an initial value in a signal amplification bus pre-charging period after temporarily storing the ath batch of global data to a register; and
transferring the (a+1)th batch of local data from the local data bus to the signal amplification bus.
2. The method of claim 1, wherein the following operations are carried out in the nth clock cycle of the synchronous timing:
reading out an address value;
decoding the address value; and
retrieving local bus data from a location corresponding to the address provided by the decoding operation.
3. The method of claim 2, wherein the ath batch of local data is put on the local data bus in the non-local data bus pre-charging period after the address value is decoded, a column select is within the address value decoding termination cycle and other signals corresponding to the column select is within the address value decoding termination cycle.
4. The method of claim 1, wherein after the transfer of the ath batch of global data from the signal amplification bus to the global data bus, further includes storing the ath batch of global data in a register within the synchronous memory.
5. The method of claim 4, wherein after the transfer of the ath batch of global data into the register, further includes outputting the ath batch of global data from the register in the (n+2)th cycle of the synchronous timing.
6. The method of claim 1, wherein the step of putting the (a+1)th batch of local data on the local data bus requires a signal developing time for transforming the (a+1)th batch of local data into the (a+1)th batch of local data pair.
7. The method of claim 6, wherein length of the signal developing time is the period between the transition of the local data bus pre-charging period into the non-local data bus pre-charging period and the transition from the non-global data transmission period into the global data transmission period.