1. A nitride read only memory cell comprising:
a silicon-germanium layer comprising a pair of sourcedrain regions;
a strained silicon layer overlying the silicon-germanium layer;
a nitride layer overlying the strained silicon layer; and
a control gate overlying the nitride layer.
2. The cell of claim 1 wherein, during operation of the cell, a channel forms in the strained silicon layer between the pair of sourcedrain regions and a first charge storage region of the nitride layer establishes a virtual sourcedrain region in the channel, the virtual sourcedrain region having a lower threshold voltage than a remaining portion of the channel.
3. The cell of claim 2 wherein at least a portion of the channel is in a vertical configuration.
4. The cell of claim 2 wherein the channel is in a planar configuration.
5. The cell of claim 1 and further including a substrate bias connection that is capable of applying a bias to the substrate.
6. The cell of claim 5 wherein the substrate bias is in a range of \u22121V to \u22122V.
7. The cell of claim 3 wherein the vertical channel configuration is two-dimensional.
8. The cell of claim 2 wherein the virtual sourcedrain region is established in response to an absence of electrons on a portion of the nitride layer.
9. The cell of claim 1 wherein the substrate is a p-type silicon material and the sourcedrain regions are an n-type silicon material.
10. The cell of claim 1 wherein the nitride layer is isolated from the strained silicon layer by a first oxide dielectric material and from the control gate by a second oxide dielectric material.
11. The cell of claim 1 wherein the strained silicon layer is formed by one of ultra-high vacuum chemical vapor deposition, ion implantation, micromechanical strain, or mechanical strain.
12. The cell of claim 1 wherein the strained silicon layer is due to a lattice mismatch between the silicon and the silicon-germanium layer with a larger lattice spacing.
13. The cell of claim 1 wherein ballistic direct injection is used to program the cell.
14. The cell of claim 1 wherein the nitride layer is part of a composite gate dielectric layer that is a composite oxide-nitride-oxide layer wherein the nitride is a charge trapping layer.
15. The cell of claim 14 wherein the gate dielectric is a composite oxide-nitride nanolaminate gate insulator.
16. The cell of claim 3 wherein the channel is less than 50 nm in length.
17. The cell of claim 3 wherein the channel is less than 100 nm in length.
18. A nitride read only memory cell comprising:
a silicon-germanium layer comprising a pair of sourcedrain regions;
a strained silicon layer formed overlying the silicon-germanium layer;
a split gate nitride layer comprising a pair of charge storage regions; and
a control gate formed overlying the nitride layer and comprising a depression formed between the pair of charge storage regions that splits the nitride layer such that the pair charge storage regions are electrically isolated from each other.
19. The cell of claim 18 wherein, during operation of the cell, a virtual sourcedrain region is established in a channel in the strained silicon layer between the pair of sourcedrain regions in response to a drain voltage being applied to a first sourcedrain region adjacent the virtual sourcedrain region.
20. The cell of claim 19 wherein the virtual sourcedrain region is established in response to a first charge storage region on the split gate nitride layer, the virtual sourcedrain region having a lower threshold voltage than a remaining portion of the channel.
21. The cell of claim 18 wherein the split gate nitride layer is part of an oxide-nitride-oxide layer.
22. The cell of claim 19 wherein the virtual sourcedrain region is established in response to a positive charge on the first charge storage region.
23. The cell of claim 18 wherein the silicon-germanium layer is formed on a silicon substrate.
24. The cell of claim 18 wherein the strained silicon layer is formed by one of ultra-high vacuum chemical vapor deposition, ion implantation, micromechanical strain, or mechanical strain.
25. A nitride read only memory cell comprising:
a pillar in a silicon-germanium layer, the pillar being defined by a plurality of trenches;
a pair of sourcedrain regions, each sourcedrain region located under a different trench;
a strained silicon layer formed overlying the silicon-germanium layer at the top of each pillar;
a pair of vertical nitride charge storage regions that are separated by the pillar; and
a control gate formed overlying the pair of vertical charge storage regions and the pillar.
26. The cell of claim 25 wherein, during operation of the cell, the pair of sourcedrain regions are linked by a two-dimensional channel that follows a surface of the pillar.
27. The cell of claim 26 wherein, during operation of the cell, a first nitride charge storage region establishes a virtual sourcedrain region in the channel adjacent to the first nitride charge storage region, the virtual sourcedrain region having a lower threshold voltage than a remaining portion of the channel
28. The cell of claim 25 wherein the pair of vertical nitride charge storage regions form a split nitride layer.
29. The cell of claim 25 wherein a depression of the control gate is formed in the trench to separate a first flash memory cell from a second flash memory cell.
30. The cell of claim 25 and further including an insulator layer under the silicon-germanium layer to form a silicon-on-insulator structure.
31. The cell of claim 25 wherein the sourcedrain regions link a plurality of flash memory cells in a virtual ground array configuration.
32. The cell of claim 25 wherein the nitride read only memory cell is a NAND flash memory cell.
33. The cell of claim 25 wherein the nitride read only memory cell is a NOR flash memory cell.
34. The cell of claim 25 wherein the cell is programmable by ballistic direct injection.
35. The cell of claim 26 wherein the channel is less than 50 nm in length.
36. The cell of claim 26 wherein the channel is less than 100 nm in length.
37. The cell of claim 25 wherein the control gate is separated from the pair of vertical charge storage regions and the pillar by an oxide dielectric material.
38. A nitride read only memory cell array comprising:
a plurality of flash memory cells coupled together through wordlines and bitlines, each cell comprising:
a silicon-germanium layer comprising a pair of sourcedrain regions;
a strained silicon layer formed overlying the silicon-germanium layer;
a nitride floating gate layer, comprising a plurality of charge storage areas, formed overlying the strained silicon layer; and
a control gate formed overlying the nitride floating gate layer.
39. The array of claim 38 wherein, during operation of each cell, the pair of source drain regions are linked by a channel in the strained silicon layer.
40. The array of claim 39 wherein, during operation of each cell, a first charge storage area establishes a virtual sourcedrain region in the channel, the virtual sourcedrain region having a lower threshold voltage than a remaining portion of the channel
41. The array of claim 38 wherein the plurality of memory cells are configured in a NAND-type architecture.
42. The array of claim 38 wherein the plurality of flash memory cells are configured in a NOR-type architecture.
43. An electronic system comprising:
a processor that generates memory control signals; and
a flash memory cell array coupled to the processor and comprising a plurality of flash memory cells coupled together through wordlines and bitlines, each cell comprising:
a silicon-germanium layer comprising a pair of sourcedrain regions;
a strained silicon layer formed overlying the silicon-germanium layer, the pair of sourcedrain regions being linked by a channel in the strained silicon layer during operation of the cell;
a nitride floating gate layer, comprising a plurality of charge storage areas, formed overlying the strained silicon layer, wherein during operation of the cell a first charge storage region of the nitride floating gate layer establishes a virtual sourcedrain region in the channel, the virtual sourcedrain region having a lower threshold voltage than a remaining portion of the channel; and
a control gate formed overlying the nitride floating gate layer.
44. A method for writing to a nitride read only memory cell comprising at least one nitride charge storage region located between a substrate having two sourcedrain regions and a control gate, the two sourcedrain regions located in a silicon-germanium layer and linked by a channel a strained silicon layer on the silicon-germanium layer, the method comprising:
creating a positive charge on the floating gate;
grounding a first sourcedrain region;
applying a gate voltage to the control gate; and
applying a drain voltage to the second sourcedrain region such that ballistic direct injection occurs in a virtual sourcedrain region of the channel adjacent a first charge storage region of the at least one nitride charge storage region.
45. The method of claim 44 and further including applying a substrate bias to the substrate.
46. The method of claim 45 wherein the substrate bias is a negative voltage.
47. The method of claim 44 wherein creating the positive charge includes over-erasing the flash memory cell.
48. A method for writing to a nitride read only memory cell comprising a gate insulator layer having at least one charge storage region in a nitride layer located between oxide dielectric layers, a silicon-germanium layer having two sourcedrain regions and a control gate overlying the gate insulator layer, the two sourcedrain regions linked by a channel in a strained silicon layer overlying the silicon-germanium layer, the method comprising:
creating a positive charge on the floating gate;
grounding a first sourcedrain region;
applying a gate voltage to the control gate; and
applying a drain voltage to the second sourcedrain region such that the channel is pinched off a predetermined distance from the second sourcedrain region and adjacent to a first charge storage region of the nitride layer.
49. A nitride read only memory cell comprising:
a silicon-germanium layer comprising a pair of sourcedrain regions separated by a channel region that is less than 100 nm in length;
a strained silicon layer overlying the silicon-germanium layer;
a split gate nitride layer comprising a pair of charge storage regions; and
a control gate overlying the gate insulator layer and comprising a depression formed between the pair of charge storage regions that splits the nitride layer such that the charge storage regions are electrically isolated.
50. The cell of claim 49 wherein, during a programming operation of the cell, a channel and a virtual sourcedrain region form in the channel region, the virtual sourcedrain region forming in response to a charge on one of the pair of charge storage regions.
51. The cell of claim 49 wherein during a programming operation, ballistic direct injection is used.
52. A nitride read only memory cell comprising:
an insulator substrate comprising an oxide material;
a silicon-germanium layer overlying the insulator substrate, the silicon-germanium layer comprising a pair of sourcedrain regions separated by a channel region;
a strained silicon layer overlying the silicon-germanium layer;
a split gate oxide-nitride-oxide layer comprising a pair of charge storage regions; and
a control gate overlying the gate insulator layer and comprising a depression formed between the pair of charge storage regions that splits the nitride layer such that the charge storage regions are electrically isolated.
53. The cell of claim 52 wherein the channel region is less than 50 nm in length.
54. The cell of claim 52 wherein the oxide-nitride-oxide layer is 15 nm thick.
55. A method for manufacturing a nitride read only memory cell, the method comprising:
forming a silicon-germanium layer on a substrate, the silicon-germanium layer comprising a pair of sourcedrain regions;
forming a strained silicon layer overlying the silicon-germanium layer;
forming a nitride layer overlying the strained silicon layer; and
forming a control gate overlying the nitride layer.
56. The method of claim 55 wherein the substrate is an insulator material such that the silicon-germanium layer forms a silicon-on-insulator structure with the substrate.
57. The method of claim 55 wherein the control gate is comprised of a doped polysilicon material.
58. A method for manufacturing a split gate nitride read only memory cell, the method comprising:
forming a silicon-germanium layer on a substrate, the silicon-germanium layer comprising a pair of sourcedrain regions;
forming a strained silicon layer overlying the silicon-germanium layer;
forming a split gate nitride layer comprising a pair of charge storage regions; and
forming a control gate overlying the gate insulator layer and between the pair of charge storage regions that splits the nitride layer such that the charge storage regions are electrically isolated.
59. The method of claim 58 wherein the pair of sourcedrain regions are separated by less than 100 nm.
60. The method of claim 58 wherein the split gate nitride layer is approximately 5 nm thick and is part of an oxide-nitride-oxide structure.
61. A method for manufacturing a split gate nitride read only memory cell, the method comprising:
forming a silicon-germanium layer on a substrate, the silicon-germanium layer comprising a pair of sourcedrain regions;
forming a strained silicon layer overlying the silicon-germanium layer;
forming an oxide-nitride-oxide composite layer comprising a pair of charge storage regions; and
forming a control gate overlying the gate insulator layer.
62. The method of claim 61 wherein the control gate is formed such that it splits the oxide-nitride-oxide composite layer and electrically isolates the pair of charge storage regions.
63. The method of claim 61 wherein the oxide-nitride-oxide composite layer is formed in a thickness of approximately 15 nm.
64. The method of claim 61 wherein the strained silicon layer comprises a channel region, between the pair of sourcedrain regions, in which a channel forms during a programming operation of the cell.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multistage flow control device, comprising:
a tubular with a plurality of one or more openings;
a plurality of seats positioned at the tubular; and
a plurality of plugs being movable relative to the tubular between at least a first position sealingly engaged with one of the plurality of seats and a second position displaced from the one of the plurality of seats, each of the plurality of plugs being movable from the first position to the second position in response to a pressure differential applied thereacross achieving a threshold value with a first of the plurality of plugs moving at a first threshold value and a second of the plurality of plugs moving at a second threshold value.
2. The multistage flow control device of claim 1, further comprising a third of the plurality of plugs moving at a third threshold value.
3. The multistage flow control device of claim 1, further comprising a plurality of biasing members with each of the plurality of biasing members biasing one of the plurality of plugs toward the first position.
4. The multistage flow control device of claim 1, wherein flow through a first of the plurality of one or more openings is prevented by the first of the plurality of plugs being in the first position and flow through the first of the plurality of one or more openings is allowed when at least the first of the plurality plugs is in the second position.
5. The multistage flow control device of claim 4, wherein flow through a second of the plurality of one or more openings is prevented by the second of the plurality plugs being in the first position and flow through the second of the plurality of one or more openings is allowed when at least the first of the plurality plugs and the second of the plurality plugs are in the second position.
6. The multistage flow control device of claim 5, wherein flow through a first flow-path between the first of the plurality plugs and a first of the plurality of seats is flowable through either the first of the plurality of one or more openings or the second of the plurality of one or more openings when the first of the plurality plugs and the second of the plurality plugs are both in the second position.
7. The multistage flow control device of claim 1, wherein a stem of the first of the plurality plugs is locatable within a cavity when the firsts of the plurality plug is in the second position.
8. The multistage flow control device of claim 7, wherein the cavity is in the second of the plurality plugs.
9. The multistage flow control device of claim 7, wherein fluid is displaced from the cavity when the stem is located within the cavity.
10. The multistage flow control device of claim 9, wherein the stem and the cavity are sized to dampen movement of the stem into and out of the cavity by restricting fluid flow rates into and out of the cavity.
11. The multistage flow control device of claim 1, wherein flow area through each of the plurality of one or more openings of the multistage flow control device is controlled by the total area of flow of the plurality of one or more openings open to flow at a given pressure differential across the multistage flow control device.
12. A method of controlling flow of fluid through a tubular, comprising:
building pressure differential across a flow control device;
moving a first plug at a first threshold value of the pressure differential;
flowing fluid through a first one or more openings in the tubular;
increasing the pressure differential across the flow control device;
moving a second plug at a second threshold value of the pressure differential; and
flowing fluid through the first one or more openings and a second one or more openings in the tubular.
13. The method of controlling flow of fluid through a tubular of claim 12, further comprising:
increasing the pressure differential across the flow control device;
moving a third plug at a third threshold pressure value of the pressure differential; and
flowing fluid through the first one or more openings, the second one or more openings and a third one or more openings in the tubular.
14. The method of controlling flow of fluid through a tubular of claim 12, further comprising damping a rate of movement of the first plug.
15. The method of controlling flow of fluid through a tubular of claim 14, further comprising displacing fluid within a cavity with the moving of a stem of the first plug into the cavity.
16. The method of controlling flow of fluid through a tubular of claim 15, further comprising restricting a rate of flow of fluid from the cavity.
17. The method of controlling flow of fluid through a tubular of claim 14, further comprising biasing at least one of the first plug and the second plug in a direction against movement caused by the pressure differential reaching the first threshold value or the second threshold value.
18. The method of controlling flow of fluid through a tubular of claim 12, further comprising decreasing pressure differential across the flow control device and moving the first plug and the second plug back to their original positions.
19. The method of controlling flow of fluid through a tubular of claim 18, further comprising damping a rate of movement of the first plug back to its original position by restricting flow of fluid into a cavity in the second plug that a portion of the first plug evacuates as the first plug is moved back toward its original position.