1. A method for measuring a two-dimensional distribution of ionizing radiation doses with high spatial resolution comprising exposing a radiation sensitive film to a pattern of ionizing radiation that is to be measured to produce a measurement film and exposing one or more radiation sensitive films to known calibrated doses of said ionizing radiation to produce one or more scaling films, simultaneously scanning said measurement film and said scaling film(s) together with an unexposed radiation sensitive film in a multiplicity of measurement channels to produce a digital image, measuring those areas of the digital image corresponding to said unexposed film and said scaling film(s) in said measurement channels, converting said digital image to a map of dose values based on a previously determined mathematical relationship between measured scanner response values for the film in said measurement channels and radiation dose and subsequently adjusting all the dose values corresponding to said digital image using a mathematical function so that the dose values in the areas of said digital image representative of said unexposed film and said scaling films are equal to the calibrated dose values to which they were exposed, wherein all of the radiation sensitive films are the same type of film wherein at least one scaling film is exposed to a radiation dose greater than the highest dose in the measurement film.
2. The method of claim 1 wherein the previously determined mathematical relationship is established by exposing at least one radiation sensitive film to a plurality of known calibrated doses of the ionizing radiation to form a calibration film, scanning said exposed film together with an unexposed radiation sensitive film on an optical scanner having a multiplicity of color measurement channels to produce a calibration digital image, measuring, in a multiplicity of color channels, those areas of the calibration digital image corresponding to the exposed and unexposed film and associating the measured responses in said areas of the calibration digital image to said known ionizing radiation doses to establish the relationship between the measured response values and the ionizing radiation doses, wherein all of the radiation sensitive films are the same type of film.
3. The method of claim 1 wherein the radiation sensitive films are radiochromic films.
4. The method of claim 3 wherein the radiochromic film contains a diacetylene.
5. The method of claim 1 wherein the number of scaling films is one.
6. The method of claim 1 wherein the number of scaling films is two.
7. The method of claim 1 wherein the number of scaling films and calibrated scaling doses is one.
8. The method of claim 1 wherein the number of scaling films and calibrated scaling doses is two.
9. The method of claim 1 wherein the radiation sensitive film has a spatial resolution of at least 1 mm.
10. The method of claim 9 wherein the spatial resolution of the radiation sensitive film is at least 0.1 mm.
11. The method of claim 10 wherein the spatial resolution of the radiation sensitive film is at least 0.01 mm.
12. The method of claim 11 wherein the spatial resolution of the radiation sensitive film is at least 0.001 mm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An on-chip voltage conversion apparatus for integrated circuits, comprising:
a first capacitor;
a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain;
a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and
a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
2. The apparatus of claim 1, wherein the first capacitor comprises a deep trench capacitor.
3. The apparatus of claim 1, wherein the first and second NFET and PFET devices are formed on a silicon-on-insulator (SOI) substrate.
4. The apparatus of claim 1, wherein actuating signals to the first and second NFET and PFET devices are applied so as to charge and discharge the first capacitor between a first magnitude corresponding to the voltage difference across the first voltage domain and a second magnitude corresponding to the voltage difference across the second voltage domain.
5. The apparatus of claim 1, wherein for a down-conversion mode operation, the high side voltage rail of the second voltage domain, V2, is an input voltage and the high side voltage rail of the first voltage domain, V1, is an output voltage, such that V2>2*V1.
6. The apparatus of claim 1, wherein for an up-conversion mode operation, the high side voltage rail of the first voltage domain, V1, is an input voltage and the high side voltage rail of the second voltage domain, V2, is an output voltage, such that V2<2*V1.
7. The apparatus of claim 4, wherein the actuating signals to the first and second NFET and PFET devices are applied in a manner so as to prevent simultaneous conduction of any NFET device and any PFET device.
8. The apparatus of claim 4, wherein an output current is proportional to a switching frequency of the actuating signals.
9. The apparatus of claim 1, wherein:
gate terminals of the first NFET and PFET devices operate entirely within the first voltage domain; and
gate terminals of the second NFET and PFET devices operate entirely within the second voltage domain.
10. The apparatus of claim 1, further comprising:
one or more additional capacitors in series with the first capacitor;
one or more pairs of additional NFET and PFET devices associated with one or more additional voltage domains for each one or more additional capacitors so as to define a voltage converter that nominally converts a voltage level of N voltage units to a voltage level of M voltage units and vice versa;
wherein N represents the total number of pairs of NFET and PFET devices, N\u22121 represents the total number of capacitors, and 1\u2266M\u2266N\u22121.
11. The apparatus of claim 10, wherein the pairs of NFET and PFET devices in each voltage domain are controlled in a manner so as to charge and discharge the associated capacitor between a first magnitude and a second magnitude, wherein for the Xth capacitor of the apparatus, the first magnitude corresponds to the voltage difference across the Xth voltage domain and the second magnitude corresponds to the voltage difference across the (X+1)th voltage domain.
12. The apparatus of claim 11, wherein the NFET and PFET devices are operated in a manner so as to prevent simultaneous conduction of any NFET device and any PFET device.
13. The apparatus of claim 10, wherein for a down-converter mode of operation, the converter serves an N-to-M down-converter.
14. The apparatus of claim 10, wherein for an up-converter mode of operation, the converter serves an M-to-N up-converter.
15. The apparatus of claim 10, wherein a first plurality of voltage levels are converted to a second plurality of voltage levels.
16. The apparatus of claim 1, wherein the first and second NFET and PFET devices are formed on bulk silicon substrates with triple well technology.
17. An on-chip voltage conversion system for integrated circuits, comprising:
a clock source having a plurality of clock phases;
a plurality of actuating signals corresponding to one of a plurality of phases; and
a plurality of voltage converters controlled by the actuating signals, with each voltage converter comprising:
a first capacitor;
a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain;
a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and
a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
18. An on-chip voltage conversion system for integrated circuits, comprising:
a clock source having a plurality of clock phases;
a plurality of actuating signals corresponding to one of a plurality of phases; and
a plurality of voltage converters controlled by the actuating signals, with each voltage converter comprising:
a first capacitor;
a first pair of NFET and PFET devices associated with a first voltage domain, with a first NFET of the first pair configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of the first voltage domain, and a first PFET of the first pair configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
a second pair of NFET and PFET devices associated with a second voltage domain, with a second NFET of the second pair configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of the second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain, and a second PFET of the second voltage domain configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain; and
one or more additional capacitors in series with the first capacitor;
one or more additional pairs of NFET and PFET devices associated with one or more additional voltage domains for each one or more additional capacitors so as to define a multiple level converter that nominally converts a voltage level of N voltage units to a voltage level of M voltage units and vice versa;
wherein N represents the total number of pairs of switching devices, N\u22121 represents the total number of capacitors, and 1\u2266M\u2266N\u22121.
19. The system of claim 18, wherein actuating signals to the pairs of NFET and PFET devices in each voltage domain are applied so as to charge and discharge the associated capacitor between a first magnitude and a second magnitude, wherein for the Xth capacitor of the apparatus, the first magnitude corresponds to the voltage difference across the Xth voltage domain and the second magnitude corresponds to the voltage difference across the (X+1)th voltage domain.
20. The system of claim 19, wherein the actuating signals to the NFET and PFET devices in each pair are applied in a manner so as to prevent simultaneous conduction of the NFET and PFET devices.
21. A method of implementing on-chip voltage conversion for integrated circuits, the method comprising:
using a first NFET device to selectively couple a first electrode of a first capacitor to a low side voltage rail of a first voltage domain;
using a first PFET device to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
using a second NFET device to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and
using a second PFET device to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
22. The method of claim 21, wherein the first capacitor comprises a deep trench capacitor.
23. The method of claim 22, wherein the first and second NFET and PFET devices are formed on a silicon-on-insulator (SOI) substrate.
24. The method of claim 21, further comprising applying actuating signals to the first and second NFET and PFET devices so as to charge and discharge the first capacitor between a first magnitude corresponding to the voltage difference across the first voltage domain and a second magnitude corresponding to the voltage difference across the second voltage domain.
25. The method of claim 24, wherein for a down-conversion mode operation, the voltage of the second voltage domain, V2, is an input voltage and the voltage of the first voltage domain, V1, is an output voltage, such that V2>2*V1.
26. The method of claim 24, wherein for an up-conversion mode operation, the voltage of the first voltage domain, V1, is an input voltage and the voltage of the second voltage domain, V2, is an output voltage, such that V2<2*V1.