1. Apparatus comprising:
at least one processor; and
at least one computer readable storage medium including instructions which when executed by the processor configure the processor to:
receive indication of an interrogation of an electronic transaction card (e-card) by an interrogating device;
responsive to the indication, authorize the e-card to respond to the interrogation only responsive to a determination that an authorized point of sale (POS) device is proximate to a location.
2. The apparatus of claim 1, wherein the instructions when executed by the processor configure the processor to determine that an authorized POS device is proximate to the location at least in part by determining that an authorized POS device is within a threshold distance of the location.
3. The apparatus of claim 1, wherein the location is a location of the e-card.
4. The apparatus of claim 1, wherein the apparatus is implemented by a consumer electronics (CE) device configured to receive the indication of the interrogation from the e-card, and the location is a location of the CE device.
5. The apparatus of claim 4, wherein the instructions when executed by the processor configure the processor to determine that an authorized POS device is proximate to the location at least in part by accessing a stored map of authorized POS device locations and comparing a location of the CE device to locations on the map, and then determining a distance between a nearest POS device on the map and the location of the CE device.
6. The apparatus of claim 1, wherein the instructions when executed by the processor configure the processor to send a message to a server reporting a denial of a transaction implicated by the interrogation.
7. The apparatus of claim 1, wherein the instructions when executed by the processor configure the processor to present on a display a message reporting a denial of a transaction implicated by the interrogation.
8. The apparatus of claim 1, wherein the apparatus is implemented by a server configured to receive from a consumer electronics (CE) device the indication of the interrogation from the e-card.
9. Non-transitory computer readable storage medium (NTCRSM) including instructions executable by a processor to configure the processor to:
receive indication of an interrogation of an electronic transaction card (e-card) by an interrogating device;
responsive to the indication, present on a display an authorized point of sale (POS) terminal map and at least one selector element selectable to send a signal to the e-card to prevent or enable the e-card to respond to the interrogation.
10. The NTCRSM of claim 9, wherein the instructions when executed by the processor configure the processor to present on the display a message reporting a denial of a transaction implicated by the interrogation.
11. The NTCRSM of claim 9, wherein the instructions when executed by the processor configure the processor to present on the display selector element selectable to send a signal to the e-card to prevent the e-card to respond to the interrogation.
12. The NTCRSM of claim 9, wherein the instructions when executed by the processor configure the processor to present on the display selector element selectable to send a signal to the e-card to enable the e-card to respond to the interrogation.
13-20. (canceled)
21. A computer-implemented method comprising:
receiving, by a computer, indication of an interrogation of an electronic transaction card (e-card) by an interrogating device;
responsive to the indication, authorizing, using a computer, the e-card to respond to the interrogation only responsive to a determination that an authorized point of sale (POS) device is proximate to a location.
22. The method of claim 21, comprising determining that an authorized POS device is proximate to the location at least in part by determining that an authorized POS device is within a threshold distance of the location.
23. The method of claim 21, wherein the location is a location of the e-card.
24. The method of claim 21, wherein the method is implemented by a consumer electronics (CE) device configured to receive the indication of the interrogation from the e-card, and the location is a location of the CE device.
25. The apparatus of claim 24, comprising determining that an authorized POS device is proximate to the location at least in part by accessing a stored map of authorized POS device locations and comparing a location of the CE device to locations on the map, and then determining a distance between a nearest POS device on the map and the location of the CE device.
26. The method of claim 21, comprising sending a message to a server reporting a denial of a transaction implicated by the interrogation.
27. The method of claim 21, comprising presenting on a display a message reporting a denial of a transaction implicated by the interrogation.
28. The method of claim 21, wherein the apparatus is implemented by a server configured to receive from a consumer electronics (CE) device the indication of the interrogation from the e-card.
29. The method of claim 21, comprising presenting on a display an authorized point of sale (POS) terminal map and at least one selector element selectable to send a signal to the e-card to prevent or enable the e-card to respond to the interrogation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
one unit or a plurality of units of first defensive wiring provided above a diffusion isolation layer formed in a substrate or a well, the first defensive wiring being arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer;
a plurality of signal wiring layers formed above the first defensive wiring; and
means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.
2. The device of claim 1, further comprising:
means for erasing secret information inside the semiconductor device or shifting the mode of the semiconductor device to a fixed mode if a change in an electrical or physical property of the first defensive wiring is captured.
3. The device of claim 1, wherein the plurality of signal wiring layers comprises:
a first signal wiring layer from which first signal wiring requiring secrecy is formed; and
a second signal wiring layer placed above the first signal wiring layer, from which second signal wiring requiring no secrecy is formed,
wherein the second signal wiring is arranged to cover the first signal wiring.
4. The device of claim 1, wherein the first defensive wiring is formed from a polysilicon layer used for formation of gates of transistor elements formed in the substrate or the well.
5. The device of claim 1, further comprising:
one unit or a plurality of units of second defensive wiring provided above the plurality of signal wiring layers, the second defensive wiring being arranged at a minimum wiring pitch allowable in fabrication to cover the entire semiconductor device; and
means for applying a predetermined signal to the second defensive wiring and capturing a change in an electrical or physical property of the second defensive wiring.
6. The device of claim 5, further comprising:
means for erasing secret information inside the semiconductor device or shifting the mode of the semiconductor device to a fixed mode if a change in an electrical or physical property of at least one of the first defensive wiring and the second defensive wiring is captured.
7. The device of claim 5, wherein a start point and an end point are placed in a layer from which the first defensive wiring is formed, and a wiring route connecting the start point and the end point is formed by combining the first defensive wiring and the second defensive wiring.
8. The device of claim 7, wherein the wiring route of the second defensive wiring recognizable by layout observation from the front of the semiconductor device is transposed using the first defensive wiring andor the plurality of signal wiring layers.
9. A semiconductor device comprising a barrier diffused layer formed in a substrate or a well so that the gap between a diffused layer constituting an element and the barrier diffused layer is a minimum gap allowable in fabrication, the barrier diffused layer being of a conductivity opposite to that of the substrate or the well, a potential reverse-biased to that of the substrate or the well being applied to the barrier diffused layer.
10. The device of claim 9, further comprising:
one unit or a plurality of units of defensive wiring provided above a signal wiring layer to be protected, the defensive wiring being arranged at a minimum wiring pitch allowable in fabrication to cover the entire semiconductor device; and
means for applying a predetermined signal to the defensive wiring and capturing a change in an electrical or physical property of the defensive wiring.
11. The device of claim 10, further comprising:
means for erasing secret information inside the semiconductor device or shifting the mode of the semiconductor device to a fixed mode if a change in an electrical or physical property of the defensive wiring is captured.
12. The device of claim 9, further comprising:
one unit or a plurality of units of first defensive wiring provided above a diffusion isolation layer formed between the diffused layer constituting an element and the barrier diffused layer, the first defensive wiring being arranged at a minimum wiring pitch allowable in fabrication to cover the diffusion isolation layer;
a plurality of signal wiring layers formed above the first defensive wiring; and
means for applying a predetermined signal to the first defensive wiring and capturing a change in an electrical or physical property of the first defensive wiring.
13. The device of claim 12, further comprising:
means for erasing secret information inside the semiconductor device or shifting the mode of the semiconductor device to a fixed mode if a change in an electrical or physical property of the first defensive wiring is captured.
14. The device of claim 12, wherein the plurality of signal wiring layers includes:
a first signal wiring layer from which first signal wiring requiring secrecy is formed; and
a second signal wiring layer provided above the first signal wiring layer, from which second signal wiring requiring no secrecy is formed,
wherein the second signal wiring is arranged to cover the first signal wiring.
15. The device of claim 12, wherein the first defensive wiring is formed from a polysilicon layer used for formation of gates of transistor elements formed in the substrate or the well.
16. The device of claim 12, further comprising:
second defensive wiring provided above the plurality of signal wiring layers, the second defensive wiring being arranged at a minimum wiring pitch allowable in fabrication to cover the entire semiconductor device; and
means for applying a predetermined signal to the second defensive wiring and capturing a change in an electrical or physical property of the second defensive wiring.
17. The device of claim 16, further comprising:
means for erasing secret information inside the semiconductor device or shifting the mode of the semiconductor device to a fixed mode if a change in an electrical or physical property of at least one of the first defensive wiring and the second defensive wiring is captured.
18. The device of claim 16, wherein a start point and an end point are placed in a layer from which the first defensive wiring is formed, and a wiring route connecting the start point and the end point is formed by combining the first defensive wiring and the second defensive wiring.
19. The device of claim 18, wherein the wiring route of the second defensive wiring recognizable by layout observation from the front of the semiconductor device is transposed using the first defensive wiring andor the plurality of signal wiring layers.