1. An information handling system providing remotely accessible in-system debugging functionality, comprising:
a first logic device;
a remote access card distinct from the first logic device, the remote access card including a network interface port, a processor, and a second logic device;
the network interface port communicatively coupled to the second logic device and configured to receive a communications link for communications with a remote device remote from the information handling system;
the second logic device including debugging logic configured to be executed by the processor;
a communication link allowing communication between the first logic device and the second logic device; and
the processor configured to receive debugging instructions from the remote device via the network interface port and, based at least on the received debugging instructions, execute the debugging logic to communicate with the first logic device via the communication link to facilitate remote debugging of the information handling system.
2. The information handling system of claim 1, wherein:
the first logic device includes one or more registers; and
facilitating remote debugging of the information handling system comprises retrieving data from the one or more registers based on the debugging instructions received from the remote device.
3. The information handling system of claim 1, wherein facilitating remote debugging of the information handling system comprises executing instructions on the first logic device based on the debugging instructions received from the remote device.
4. The information handling system of claim 1, wherein the processor is configured to receive debugging instructions from the remote device via the network interface port and, based at least on the received debugging instructions, execute the debugging logic to facilitate emulation of the first logic device.
5. The information handling system of claim 1, wherein:
the first logic device comprises a chip or chipset; and
the second logic device comprises a field programmable gate array (FPGA).
6. The information handling system of claim 1, wherein the processor includes firmware configured to execute the debugging logic associated with the second logic device.
7. The information handling system of claim 6, wherein:
the first logic device includes one or more registers; and
the firmware is configured to:
receive an interrupt notification from the first logic device; and
in response to receiving the interrupt notification, instruct the second logic device to retrieve data from the one or more registers.
8. The information handling system of claim 7, wherein the firmware is configured to, in response to receiving the interrupt notification, instruct the second logic device to retrieve a register dump defining the status of the information handling system.
9. The information handling system of claim 1, wherein:
the first logic device is located on a motherboard;
the remote access card is plugged into the motherboard by a plurality of pin connections; and
the communication link allowing communication between the first logic device and the second logic device is routed through a subset of one or more of the plurality of pin connections.
10. The information handling system of claim 1, further comprising access management logic operable to define multiple levels of access for various users of the information handling system for utilizing the debugging logic.
11. A remote access card for facilitating remotely accessible in-system debugging of an information handling system having a first logic device distinct from the remote access card, the remote access card comprising:
a processor;
a network interface port configured to receive a communications link for communications with a remote device;
a second logic device including debugging logic configured to be executed by the processor;
one or more connectors configured to provide a communication link between the second logic device and the first logic device distinct from the remote access card; and
the processor configured to remotely receive debugging instructions via the network interface port and, based at least on the received debugging instructions, execute the debugging logic on the second logic device to communicate with the first logic device via the communication link to facilitate remote debugging of the information handling system.
12. The remote access card of claim 11, wherein:
the first logic device includes one or more registers; and
facilitating remote debugging of the information handling system comprises retrieving data from the one or more registers based on the remotely received debugging instructions.
13. The remote access card of claim 11, wherein facilitating remote debugging of the information handling system comprises executing instructions on the first logic device based on the remotely received debugging instructions.
14. The remote access card of claim 11, wherein:
the first logic device comprises a chip or chipset; and
the second logic device comprises a field programmable gate array (FPGA).
15. The remote access card of claim 11, wherein the processor includes firmware configured to execute the debugging logic on the second logic device.
16. The remote access card of claim 15, wherein:
the first logic device includes one or more registers; and
the firmware is configured to:
receive an interrupt notification from the first logic device; and
in response to receiving the interrupt notification, instruct the second logic device to retrieve data from the one or more registers.
17. The remote access card of claim 16, wherein the firmware is configured to, in response to receiving the interrupt notification, instruct the second logic device to retrieve a register dump defining the status of the information handling system.
18. The remote access card of claim 11, wherein:
the first logic device is located on a motherboard;
the one or more connectors for providing a communication link between the second logic device and the first logic device comprise one or more pin connectors
19. The remote access card of claim 11, further comprising access management logic operable to define multiple levels of access for various users for utilizing the debugging logic.
20. A method for facilitating remotely accessible in-system debugging of an information handling system, comprising:
receiving at a processor associated with a remote access card an interrupt notification from a first logic device distinct from the remote access card and including one or more registers;
in response to receiving the interrupt notification, automatically instructing a second logic device of the remote access card to retrieve data from the one or more registers of the first logic device via a communications link between the second logic device and the first logic device;
receiving the data from the one or more registers of the first logic device; and
providing remote access to the data via a communications network.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A driving device for a display apparatus, comprising:
display driving circuit element regions, which are physically separated for a plurality of display data, respectively; and, in each of the display driving circuit element regions, at least:
a display data capturing portion for capturing display data corresponding to the region;
a holding portion for latching the captured display data for a predetermined period of time;
a reference voltage generating portion for generating a predetermined number of reference voltages for gray-scale display; and
a selecting portion for selecting a reference voltage corresponding to the latched display data from the generated reference voltages for gray-scale display,
wherein the reference voltage selected for each of the plurality of display data is output to the display apparatus as a display driving signal.
2. A driving device for a display apparatus according to claim 1, wherein the display data capturing portion, the holding portion, the reference voltage generating portion and the selecting portion are physically separated in each of the display driving circuit element regions.
3. A driving device for a display apparatus according to claim 2, wherein the driving device for the divided display apparatus is formed of a rectangular semiconductor device, and wherein the display driving circuit element regions are aligned in parallel in a direction of a short side of the rectangular semiconductor device.
4. A driving device for a display apparatus according to claim 3, wherein, in each of the display driving circuit element regions, the display data capturing portion, the holding portion, the reference voltage generating portion and the selecting portion are aligned in parallel in the direction of the short side of the rectangular semiconductor device.
5. A driving device for a display apparatus according to any one of claims 1 to 4, wherein the plurality of display data are classified according to color components, and the display driving circuit element regions are separated for each of the color components, respectively.
6. A driving device for a display apparatus according to claim 5, wherein the reference voltage generating portion includes three voltage correcting portions physically separated for three primary color components, respectively, and each of the voltage correcting portions generates a plurality of reference voltages for gray-scale display which are -corrected for the color component corresponding to the voltage correcting portion by using input halftone reference voltages.
7. A driving device for a display apparatus according to claim 6, wherein each of the voltage correcting portions includes a plurality of resistance elements which have predetermined resistance ratios for -correcting the input halftone reference voltages and which are connected in series.
8. A driving device for a display apparatus according to claim 5, further comprising, in each of the separate display driving circuit element regions separated for the color components, respectively:
data input terminals each for inputting display data corresponding to the color component corresponding to the region;
reference power supply terminals each for inputting a halftone reference voltage; and
output terminals each for outputting an analog value of a -corrected reference voltage for gray-scale display.
9. A display apparatus comprising a driving device for a display apparatus according to any one of claims 1 to 4.
10. A display apparatus comprising a driving device for a display apparatus according to claims 5.
11. A display apparatus comprising a driving device for a display apparatus according to claims 6.
12. A display apparatus comprising a driving device for a display apparatus according to claims 7.
13. A display apparatus comprising a driving device for a display apparatus according to claims 8.