1. A semiconductor memory device, comprising:
a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines;
a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels; and
a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.
2. The semiconductor memory device as recited in claim 1, wherein the normal driving voltage compensator includes:
a normal driving voltage discharge driver configured to pull down the normal driving voltage terminal when the voltage level of the normal driving voltage terminal is higher than a first target normal driving voltage level; and
a normal driving voltage charge driver configured to pull up the normal driving voltage terminal when the voltage level of the normal driving voltage terminal is lower than a second target normal driving voltage level.
3. The semiconductor memory device as recited in claim 1, wherein the bit line sense amplifier includes:
a bit line sense amplifying unit configured to sense and amplify the data applied to the bit lines; and
a voltage line driving unit configured to drive voltage lines of the bit line sense amplifier using the normal driving voltage or the overdriving voltage.
4. The semiconductor memory device as recited in claim 1, wherein the discharge enable signal generator includes:
a voltage detecting unit configured to detect the overdriving voltage level to output a plurality of detection signals, levels of which are determined according to the detection result; and
an activation period adjusting unit configured to adjust the activation period of the discharge enable signal according to the detection signals.
5. The semiconductor memory device as recited in claim 4, wherein the voltage detecting unit includes:
a voltage dividing unit configured to divide the overdriving voltage level by a plurality of ratios to output a plurality of divided voltages having different levels; and
a voltage comparing unit configured to compare a reference voltage corresponding to a target overdriving voltage level with the plurality of divided voltages to output the plurality of detection signals.
6. The semiconductor memory device as recited in claim 5, wherein the voltage dividing unit includes a plurality of resistors connected in series between an overdriving voltage terminal and a ground terminal and defining a predefined resistance, the plurality of divided voltages being output at connection nodes of the resistors.
7. The semiconductor memory device as recited in claim 5, wherein the voltage comparing unit includes a plurality of comparators each configured to compare the reference voltage with a respective one of the plurality of divided voltages to output the plurality of detection signals, levels of which are determined according to the comparison result.
8. The semiconductor memory device as recited in claim 4, wherein the activation period adjusting unit outputs the discharge enable signal having a longer activation period as a larger number of the detection signals are activated.
9. The semiconductor memory device as recited in claim 4, wherein the activation period adjusting unit outputs the discharge enable signal having a shorter activation period as a smaller number of the detection signals are activated.
10. The semiconductor memory device as recited in claim 5, wherein the voltage dividing unit includes first to fourth resistors connected in series between an overdriving voltage terminal and a ground terminal and each resistor having a predefined resistance;
a first divided voltage is output at a connection node of the first resistor and the second resistor;
a second divided voltage is output at a connection node of the second resistor and the third resistor; and
a third divided voltage is output at a connection node of the third resistor and the fourth resistor.
11. The semiconductor memory device as recited in claim 10, wherein the voltage comparing unit includes:
a first comparator configured to compare the first divided voltage with the reference voltage to output a first detection signal;
a second comparator configured to compare the second divided voltage with the reference voltage to output a second detection signal; and
a third comparator configured to compare the third divided voltage with the reference voltage to output a third detection signal.
12. The semiconductor memory device as recited in claim 11, wherein the activation period adjusting unit includes:
a first output unit configured to output the discharge enable signal having an activation period for a first time interval when the first detection signal is activated and the second and third detection signals are deactivated;
a second output unit configured to output the discharge enable signal having an activation period for a second time interval longer than the first time interval when the first and second detection signals are activated and the third detection signal is deactivated; and
a third output unit configured to output the discharge enable signal having an activation period for a third time interval longer than the second time interval when the first to third detection signals are activated.
13. The semiconductor memory device as recited in claim 12, wherein the first output unit includes:
a first NAND gate configured to perform a NAND operation on the first detection signal, an inverted signal of the second detection signal, and an inverted signal of the third detection signal;
a first delay configured to delay an inverted signal of an output signal of the first NAND gate for the first time interval;
a first NOR gate configured to perform a NOR operation on an inverted signal of an output signal of the first delay and the inverted signal of an output signal of the first NAND gate; and
a first switch configured to output an inverted signal of an output signal of the first NOR gate as the discharge enable signal in response to the inverted signal of an output signal of the first NAND gate.
14. The semiconductor memory device as recited in claim 13, wherein the second output unit includes:
a second NAND gate configured to perform a NAND operation on the first detection signal, the second detection signal, and an inverted signal of the third detection signal;
a second delay configured to delay an inverted signal of an output signal of the second NAND gate for the second time interval;
a second NOR gate configured to perform a NOR operation on an inverted signal of an output signal of the second delay and the inverted signal of an output signal of the second NAND gate; and
a second switch configured to output an inverted signal of an output signal of the second NOR gate as the discharge enable signal in response to the inverted signal of an output signal of the second NAND gate.
15. The semiconductor memory device as recited in claim 14, wherein the third output unit includes:
a third NAND gate configured to perform a NAND operation on the first to third detection signals;
a third delay configured to delay an inverted signal of an output signal of the third NAND gate for the third time interval;
a third NOR gate configured to perform a NOR operation on an inverted signal of an output signal of the third delay and the inverted signal of an output signal of the third NAND gate; and
a third switch configured to output an inverted signal of an output signal of the third NOR gate as the discharge enable signal in response to the inverted signal of an output signal of the third NAND gate.
16. A semiconductor memory device, comprising:
a bit line sense amplifier configured to sense and amplify data applied to bit lines;
a voltage line driver configured to drive voltage lines of the bit line sense amplifier to a normal driving voltage or an overdriving voltage;
a normal driving voltage charge driver configured to pull up a normal driving voltage terminal when a voltage level of the normal driving voltage terminal is lower than a first target normal driving voltage level;
a normal driving voltage discharge driver configured to pull down the normal driving voltage terminal when the voltage level of the normal driving voltage terminal is higher than a second target normal driving voltage level during an activation period of a discharge enable signal;
a voltage detector configured to detect the overdriving voltage level to output a plurality of detection signals, levels of which are determined according to the detection result; and
an activation period adjusting unit configured to adjust the activation period of the discharge enable signal according to the detection signals.
17. The semiconductor memory device as recited in claim 16, wherein the voltage detector includes:
a voltage dividing unit configured to divide the overdriving voltage level by a plurality of ratios to output a plurality of divided voltages having different levels; and
a voltage comparing unit configured to compare a reference voltage corresponding to a target overdriving voltage level with the plurality of divided voltages to output the plurality of detection signals.
18. The semiconductor memory device as recited in claim 17, wherein the voltage dividing unit includes a plurality of resistors connected in series between an overdriving voltage terminal and a ground terminal and defining a predefined resistance, the plurality of divided voltages being output at connection nodes of the resistors.
19. The semiconductor memory device as recited in claim 17, wherein the voltage comparing unit includes a plurality of comparators each configured to compare a reference voltage with a respective one of the plurality of divided voltages to output the plurality of detection signals.
20. The semiconductor memory device as recited in claim 16, wherein the activation period adjusting unit outputs the discharge enable signal having a longer activation period as a larger number of the detection signals are activated.
21. The semiconductor memory device as recited in claim 16, wherein the activation period adjusting unit outputs the discharge enable signal having a shorter activation period as a smaller number of the detection signals are activated.
22. The semiconductor memory device as recited in claim 17, wherein the voltage dividing unit includes first to fourth resistors connected in series between an overdriving voltage terminal and a ground terminal and each resistor having a predefined resistance;
a first divided voltage is output at a connection node of the first resistor and the second resistor;
a second divided voltage is output at a connection node of the second resistor and the third resistor; and
a third divided voltage is output at a connection node of the third resistor and the fourth resistor.
23. The semiconductor memory device as recited in claim 22, wherein the voltage comparing unit includes:
a first comparator configured to compare the first divided voltage with the reference voltage to output a first detection signal;
a second comparator configured to compare the second divided voltage with the reference voltage to output a second detection signal; and
a third comparator configured to compare the third divided voltage with the reference voltage to output a third detection signal.
24. The semiconductor memory device as recited in claim 23, wherein the activation period adjusting unit includes:
a first output unit configured to output the discharge enable signal having an activation period for a first time interval when the first detection signal is activated and the second and third detection signals are deactivated;
a second output unit configured to output the discharge enable signal having an activation period for a second time interval longer than the first time interval when the first and second detection signals are activated and the third detection signal is deactivated; and
a third output unit configured to output the discharge enable signal having an activation period for a third time interval longer than the second time interval when the first to third detection signals are activated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for preparing an integrated egg-filled food product comprising:
pre-heating a cooking container having a flat cooking surface;
depositing in the cooking container on the flat cooking surface an at least partially cooked, frozen egg filling;
depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling and contacts the flat cooking surface;
cooking the partially encased egg filling and batter while:
maintaining a surface of the egg filling in contact with the flat cooking surface, and
gelatinizing the batter about the egg filling to form an egg-filled food product;
whereby the surface of the egg filling in contact with the flat cooking surface remains not encased; and
freezing the egg-filled food product.
2. A method for preparing an integrated egg-based food product comprising:
pre-heating a cooking container having a cooking surface;
depositing in the cooking container on the cooking surface an at least partially cooked, frozen egg filling;
depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling and contacts the cooking surface;
cooking the partially encased egg filling and batter while:
maintaining a surface of the egg filling in contact with the cooking surface, and
gelatinizing the batter about the egg filling to form an integrated food product;
whereby the surface of the egg filling in contact with the cooking surface remains uncovered; and
freezing the integrated food product.
3. The method of claim 2 wherein the step of depositing the frozen egg filling comprises depositing in the cooking container on the cooking surface an at least partially cooked, frozen circular shaped egg filling.
4. The method of claim 2 wherein at least part of the cooking surface is flat and the step of depositing the frozen egg filling comprises depositing in the cooking container on the flat cooking surface an at least partially cooked, frozen circular shaped egg filling.
5. The method of claim 2 wherein the step of depositing the batter comprises depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling, contacts the cooking surface, and forms a circular shape.
6. The method of claim 2 wherein the step of depositing the batter comprises depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling, contacts the cooking surface, and forms a circular shape of diameter from about 10 cm (about 2 in.) to about 20 cm (about 8 in.).
7. The method of claim 2 wherein the step of depositing the batter comprises depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling, contacts the cooking surface, forms a circular shape of diameter from about 10 cm (about 2 in.) to about 20 cm (about 8 in.) and thickness about 12 mm (about 0.5 in.) to about 100 mm (about 4 in.) at about the center.
8. The method of claim 2 wherein the step of cooking the partially encased egg filling and batter comprises cooking the partially encased egg filling and batter while:
maintaining a surface of the egg filling in contact with the cooking surface, and
gelatinizing the batter about the egg filling to form an integrated food product being an open face egg sandwich.
9. The method of claim 2 wherein the cooking surface is flat and the depositing steps comprise: depositing in the cooking container on the flat cooking surface an at least partially cooked, frozen egg filling; and depositing in the cooking container a non-yeast leavened batter whereby the batter covers and partially encases the egg filling and contacts the flat cooking surface.
10. The method of claim 2 wherein the pre-heating step comprises pre-heating a cooking container having a cooking surface such that the cooking surface is heated to about 205 degrees C. (about 400 degrees F.).
11. The method of claim 2 wherein the step of depositing the egg filling comprises depositing in the cooking container on the cooking surface an at least partially cooked, frozen simulated egg patty.
12. The method of claim 2 wherein the step of depositing the egg filling comprises depositing in the cooking container on the cooking surface an at least partially cooked, frozen egg filling having a pH about 6.6 plus or minus 0.1.
13. A method for preparing an integrated egg-based food product comprising:
pre-heating a cooking container having a cooking surface;
depositing in the cooking container on the cooking surface an at least partially cooked, frozen egg filling so that a contacting portion of the filling contacts the cooking surface;
depositing in the cooking container a non-yeast leavened batter whereby the batter covers the egg filling excluding the contacting portion and the egg filling contacting portion remains in contact with the cooking surface;
cooking the egg filling and batter while:
maintaining the egg filling contacting portion in contact with the cooking surface, and
gelatinizing the batter about the egg filling to form an integrated food product whereby the contacting portion of the egg filling in contact with the cooking surface remains uncovered by the gelatinizing batter; and
freezing the integrated food product.
14. The method of claim 13 wherein the gelatinizing step comprises gelatinizing the batter about the egg filling to form an integrated food product whereby the contacting portion of the egg filling in contact with the cooking surface remains uncovered by the gelatinizing batter to form an integrated food product being an open face egg sandwich.