1. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
receiving a request via a process thread having a first memory map associated therewith;
changing a privilege level to a level that allows a map change;
performing the map change to associate a second memory map with the process thread, the second memory map providing different memory access with respect to the first memory map; and
restoring the privilege level to a level that does not allow a map change.
2. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
associating first and second address maps with a process, wherein at least the second address map includes a mapping that maps a virtual address to a physical address that is larger than the largest possible virtual memory address;
receiving a request from a thread of the process to change from the first address map to the second address map;
changing the first address map to the second address map; and
using the mapping to access data at a physical memory location having a physical address that is larger than the largest possible virtual memory address.
3. At least one computer-readable medium, having computer-executable instructions which when executed perform steps, comprising:
associating first and second address maps with a process, wherein the second address map provides different memory access with respect to the first memory map;
running trusted code with the first map;
switching to the second map prior to running a first set of untrusted code without switching the process; and
returning to the first map after completion of the untrusted code.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a gate electrode, comprising the steps of;
forming a lower amorphous silicon layer using silane (SiH4) gas and nitrous oxide (N2O) gas;
forming an upper amorphous silicon layer on the lower amorphous silicon layer; and
crystallizing the lower and upper amorphous silicon layers through a thermal process.
2. The method of forming the gate electrode of claim 1, wherein the lower polysilicon layer, which is crystallized after performing the thermal process, has the grain size which is more uniform and denser than that of the upper polysilicon layer due to a partial oxidation of the lower amorphous silicon layer caused by nitrous oxide (N2O) gas.
3. The method of forming the gate electrode of claim 1, wherein the lower amorphous silicon layer is formed through a lower pressure chemical vapor deposition process.
4. The method of forming the gate electrode of claim 3, wherein the lower pressure chemical vapor deposition process is performed at a temperature of 700 to 900\xb0 C. and a pressure of 0.5 to 2.0 Torr.
5. The method of forming the gate electrode of claim 1, wherein the upper amorphous silicon layer is formed through a lower pressure chemical vapor deposition process.
6. The method of forming the gate electrode of claim 5, wherein the lower pressure chemical vapor deposition process is performed at a temperature of 500 to 650\xb0 C. and a pressure of 0.5 to 2.0 Torr.
7. The method of forming the gate electrode of claim 5, wherein the lower pressure chemical vapor deposition process is performed under an atmosphere of silane (SiH4) gas and phosphine (PH3) gas.