1. An electro-optic device, comprising:
a plurality of pixel electrodes arranged in a matrix, the plurality of pixel electrodes including a first pixel electrode and a second pixel electrode that is closest to the first pixel electrode, a space being formed between the first pixel electrode and the second pixel electrode;
an electro-optic layer located over the first pixel electrode, second pixel electrode and the space, the electro-optic layer including a plurality of charged particles; and
an opposed electrode located over the electro-optic layer and facing the first pixel electrode, the second pixel electrode and the space,
wherein the plurality of charged particles includes first particles which are positively charged and second particles which are negatively charged, and
wherein dG is equal to or greater than 110, and is equal to or less than 310 when d is a distance between a first edge of the first pixel electrode and a second edge of the second pixel electrode, the first edge being closer to the second pixel electrode than any other edge of the first pixel electrode, and the second edge being closer to the first pixel electrode than any other edge of the second pixel electrode, and G is a gap formed between the opposed electrode and at least one of the first pixel electrode and the second pixel electrode.
2. The electro-optic device according to claim 1,
wherein the electro-optic layer includes a dispersion medium dispersing the first particles and the second particles.
3. The electro-optic device according to claim 2,
wherein the electro-optic layer includes a plurality of microcapsules, and
wherein each of the plurality of microcapsules encapsulates the dispersion medium, the first particles, and the second particles.
4. The electro-optic device according to claim 3,
wherein the electro-optic layer includes a binder that fixes the positions of the microcapsules.
5. The electro-optic device according to claim 1,
wherein the first particles exhibit black in color, and the second particles exhibit white in color.
6. The electro-optic device according to claim 1, further comprising:
a first substrate; and
a second substrate facing the first substrate
wherein the plurality of pixel electrodes are disposed between the first substrate and the electro-optic layer and the opposed electrode is disposed between the second substrate and the electro-optic layer.
7. The electro-optic device according to claim 1,
wherein the distance d is in a range from 5 \u03bcm to 15 \u03bcm.
8. The electro-optic device according to claim 1,
wherein the opposed electrode has light permeability.
9. The electro-optic device according to claim 8,
wherein the opposed electrode is made of ITO.
10. The electro-optic device according to claim 1,
wherein each of the plurality of the pixel electrodes is rectangular in shape.
11. The electro-optic device according to claim 1, further comprising:
a plurality of scanning lines extending in a first direction;
a plurality of data lines extending in a second direction intersecting with the first direction; and
a plurality of switching elements, each of the plurality of switching elements controlling conductivity between one of the plurality of data lines and one of the plurality of pixel electrodes according a scanning signal supplied through one of the plurality of scanning lines.
12. The electro-optic device according to claim 11,
wherein the plurality of switching elements includes a first switching element electrically connected to the first pixel electrode and a second switching element electrically connected to the second pixel electrode, and
wherein one of the plurality of scanning lines is electrically connected to the first switching element and the second switching element.
13. The electro-optic device according to claim 11,
wherein the plurality of switching elements includes a first switching element electrically connected to the first pixel electrode and a second switching element electrically connected to the second pixel electrode, and
wherein one of the plurality of data lines is electrically connected to the first switching element and the second switching element.
14. The electro-optic device according to claim 11, further comprising:
a plurality of power supply lines;
a plurality of capacitors, each of the plurality of capacitors being disposed between one of the plurality of pixel electrodes and one of the plurality of power supply lines.
15. The electro-optic device according to claim 1,
wherein the first particles and the second particles positioned between the opposed electrode and the space move depending on an electric field caused by a difference in electric potentials of the opposed electrode and the first pixel electrode, or a difference in electric potentials of the opposed electrode and the second pixel electrode.
16. The electro-optic device according to claim 1,
wherein the first particles and the second particles positioned between the opposed electrode and the space move depending on an electric field caused by a difference in electric potentials of the first pixel electrode and the second pixel electrode.
17. An electronic instrument comprising the electro-optic device according to claim 1.
18. An electro-optic device, comprising:
pixel electrodes in a matrix, the pixel electrodes including a first pixel electrode and a second pixel electrode disposed adjacent the first pixel electrode with a space therebetween;
an electro-optic layer disposed over the first pixel electrode, second pixel electrode and the space, the electro-optic layer including charged particles; and
an opposed electrode disposed over the electro-optic layer and facing the first pixel electrode, the second pixel electrode and the space,
wherein the charged particles include positively charged first particles and negatively charged second particles, and
wherein 310 \u2267dG \u2267110, d being a distance between a first edge of the first pixel electrode and a second edge of the second pixel electrode, the first edge being adjacent the second edge, and G being a gap between the opposed electrode and at least one of the first and second pixel electrodes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for altering the semiconductor characteristics of a semiconductor element formed on a substrate, the method comprising:
directing an energy beam at the semiconductor element, wherein the energy beam is substantially absorbed by a first portion of the semiconductor element;
thinning the substrate under the semiconductor element; and
the step of directing an energy beam at the semiconductor element including directing the energy beam at the first portion of the semiconductor element through the substrate, wherein the energy beam is substantially transmitted through the substrate;
wherein the semiconductor element comprises:
a source region;
a drain region;
a channel region between the source region and the drain region;
a gate oxide formed over the channel region; and
a gate formed over the gate oxide, wherein the first portion of the semiconductor element comprises the gate and wherein the energy beam is substantially transmitted through the channel region; and
wherein the energy beam causes the source region and the drain region to merge so as to form an always-on current path in the semiconductor element.
2. The method of claim 1, wherein the energy beam is produced by a CO2 laser.
3. The method of claim 1, wherein the energy beam is produced by a YAG laser.
4. The method of claim 3, wherein the energy beam has a wavelength of greater than 1.2 \u03bcm.
5. The method of claim 1, wherein the energy beam is produced by a laser ablation system for repairing defects in photomasks.
6. The method of claim 1, further comprising:
forming a passivation layer over the semiconductor element on the substrate, and
mounting a support structure on the passivation layer.
7. The method of claim 6, wherein the support structure comprises an unprocessed wafer having an oxide layer, and wherein mounting the support structure comprises covalently bonding the oxide layer of the unprocessed wafer to the passivation layer.
8. The method of claim 6, wherein the support structure comprises a processed wafer having an oxide layer, and wherein mounting the support structure comprises covalently bonding the oxide layer of the processed wafer to the passivation layer.
9. The method of claim 6, wherein mounting the support structure comprises using an adhesive to attach the support structure to the passivation layer.
10. The method of claim 6, wherein thinning the backside of the processed wafer comprises a grinding operation.
11. The method of claim 6, wherein thinning the backside of the processed wafer comprises a chemical-mechanical polishing (CMP) operation.
12. The method of claim 6, wherein thinning the backside of the processed wafer comprises an etch process.
13. The method of claim 1, wherein thinning the backside of the processed wafer comprises:
forming a resist layer on the backside of the processed wafer, the resist layer comprising an aperture under the transistor; and
etching the processed wafer through the aperture.
14. The method of claim 13, wherein etching the processed wafer comprises performing an anisotropic etch process.
15. The method of claim 13, wherein etching the processed wafer comprises performing an isotropic etch process.
16. The method of claim 1, wherein the substrate comprises a silicon wafer.
17. The method of claim 1, wherein the substrate comprises a gallium arsenide wafer.
18. The method of claim 1, wherein the substrate comprises an insulating plate.
19. The method of claim 1, wherein the substrate comprises an amorphous silicon layer.
20. The method of claim 1, wherein the gate comprises a metal layer.
21. The method of claim 1, wherein the gate comprises a first silicide layer.
22. The method of claim 21, wherein the source region comprises a second silicide layer, and wherein the drain comprises a third suicide layer, the first, second, and third silicide layers being formed using a salicide process, wherein the first portion of the semiconductor element comprises the second and third silicide layers.
23. The method of claim 22, wherein the first, second, and third silicide layers comprise titanium silicide.