What is claimed is:
1. An electric power steering apparatus comprising:
a motor drive circuit for PWM-driving an electric motor to generate a steering assist torque corresponding to a steering torque, the motor drive circuit including:
a bridge circuit formed by a plurality of active elements connected together;
a first voltage step up circuit for stepping up a line voltage of the electric power steering apparatus;
a second voltage step-up circuit connected in series with the first voltage for stepping up an output voltage from the first voltage step-up circuit; and
a predrive circuit connected in series with the bridge circuit and the second voltage step-up circuit for driving active elements at a positive potential of the active elements with an output voltage from the second voltage step-up circuit supplied to the predrive circuit.
2. An electric power steering apparatus comprising:
a motor drive circuit for PWM-driving an electric motor to generate a steering assist torque corresponding to a steering torque, the motor drive circuit including:
a bridge circuit formed by a plurality of active elements connected together;
a predrive circuit connected with the bridge circuit for driving active elements at a positive potential of the active elements;
a first power supply for supplying a first voltage to the bridge circuit; and
a second power supply provided separately from the first power supply for exclusive use with the predrive circuit for supplying a second voltage solely to the predrive circuit.
3. An electric power steering apparatus according to claim 2, wherein the motor drive circuit further comprises a voltage step-up circuit disposed between the second power supply and the predrive circuit for stepping up the second voltage from the second power supply before the second voltage is supplied to the predrive circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of determining a fail string for a device comprising the steps of:
determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses;
executing a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test;
determining a fail string for the device including passfail results for the test pattern; and
combining the passfail results in the fail string.
2. The method of claim 1, wherein the portion of the address space to be tested corresponds to a number of addresses comprising each test pattern.
3. The method of claim 1, wherein the test pattern includes a single address.
4. The method of claim 3, further comprising the steps of:
holding the test pattern at the first potential during a first test, yielding in a passfail result; and
holding the test pattern at the second potential during a second test, yielding in a passfail result.
5. The method of claim 1, further comprising the step of executing the test for the test pattern, wherein the test pattern is a combination of at least one address.
6. The method of claim 1, wherein the step of determining the test pattern further includes the step of determining at least one x address and at least one y address according to a targeted fail type, wherein the targeted fail type is identified using a subset of the addresses in the address space.
7. The method of claim 1, further comprising the step of generating a pseudo compressed bitmap comprising a plurality of cells, wherein each cell is one of a passing cell and a failing cell.
8. The method of claim 7, wherein the failing cell manifests itself as a fail in the passfail results for every test pattern and the passing cell has at least one pass result for at least one test pattern.
9. The method of claim 1, further comprising the step of generating a pareto.
10. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating a pseudo compressed bitmap for a device, the method steps comprising:
determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses;
executing a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test;
determining a fail string for the device including passfail results for the test pattern; and
generating a pseudo compressed bitmap by combining each passfail result according to a Boolean AND function.
11. The method of claim 10, wherein the portion of the address space to be tested corresponds to a number of addresses comprising each test pattern.
12. The method of claim 10, wherein the test pattern includes a single address.
13. The method of claim 12, further comprising the steps of;
holding the test pattern at the first potential during a first test, yielding in a passfail result; and
holding the test pattern at the second potential during a second test, yielding in a passfail result.
14. The method of claim 10, further comprising the step of executing the test for the test pattern, wherein the test pattern is a combination of at least one address.
15. The method of claim 10, wherein the step of determining the test pattern further includes the step of determining at least one x address and at least one y address according to a targeted fail type, wherein the targeted fail type is identified using a subset of the addresses in the address space.
16. The method of claim 10, wherein the pseudo compressed bitmap comprises a plurality of cells, wherein each cell is one of a passing cell and a failing cell.
17. The method of claim 16, wherein the failing cell manifests itself as a fail in the passfail results for every test pattern and the passing cell has at least one pass result for at least one test pattern.
18. A method of generating a pseudo compressed bitmap for a device comprising the steps of:
generating a pseudo compressed bitmap by combining a plurality of passfail results according to a Boolean AND function;
displaying the pseudo compressed bitmap wherein the passfail results correspond to at least one X address pin and one Y address pin, and wherein each address pin corresponds to a plurality of passfail results.
19. The method of claim 18, wherein every combination of a test pattern including at least one address is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test.