Author: claimsbot

1. An electronic device, comprising:
a substrate; and
a thin film transistor formed over the substrate, the thin film transistor comprising a channel, a gate electrode, an insulating layer, a source, and a drain, the insulating layer being interposed between the channel and the gate electrode,
wherein the channel comprises carbon nanotubes and an organic semiconductor material.
2. The device of claim 1, wherein the electronic device comprises a display device.
3. The device of claim 1, wherein the carbon nanotubes and the organic semiconductor material are substantially homogeneously distributed throughout the channel.
4. The device of claim 1, wherein the carbon nanotubes and the organic semiconductor material are non-homogeneously distributed within the channel.
5. The device of claim 1, wherein the channel comprises a first layer comprising the carbon nanotubes, and a second layer comprising the organic semiconductor material.
6. The device of claim 5, wherein the second layer is interposed between the first layer and the insulating layer.
7. The device of claim 5, wherein the first layer is interposed between the second layer and the insulating layer.
8. The device of claim 5, wherein the first layer further comprises the organic semiconductor material.
9. The device of claim 5, wherein the second layer is substantially free of the carbon nanotubes.
10. The device of claim 9, wherein the second layer is thinner than about a half of the thickness of the first layer.
11. The device of claim 9, wherein the first layer is thinner than about a half of the thickness of the second layer.
12. The device of claim 5, wherein the first layer has a thickness of less than about 5 \u03bcm.
13. The device of claim 1, wherein the channel further comprises one or more materials selected from the group consisting of Au, Pt, Si, Ag, Fe, Ni, Co, and alloys comprising one or more of the foregoing elements.
14. The device of claim 1, wherein at least part of the carbon nanotubes are coated with one or more materials selected from the group consisting of Au, Pt, Si, Ag, Fe, Ni, Co, and alloys comprising one or more of the foregoing elements.
15. The device of claim 1, wherein the carbon nanotubes comprise at least one form selected from the group consisting of single-walled carbon nanotubes, multi-walled carbon nanotubes, and rope nanotubes.
16. The device of claim 1, wherein the carbon nanotubes comprise at least one structure selected from the group consisting of a zigzag structure, an armchair structure, and a chiral structure.
17. The device of claim 1, wherein the carbon nanotubes have a diameter about 200 nm or less.
18. The device of claim 1, wherein the organic semiconductor material comprises one or more compounds selected from the group consisting of pentacene, oligo-thiophene, poly(alkyl-thiophene), and poly(thienylenevinylene).
19. The device of claim 1, wherein the gate electrode is interposed between the insulating layer and the substrate, wherein a first portion of the insulating layer is interposed between the substrate and the source, wherein a second portion of the insulating layer is interposed between the substrate and the drain, wherein a third portion of the insulating layer is interposed between the gate electrode and the channel, and wherein both the source and the drain contact the channel.
20. The device of claim 1, wherein the channel has a charge mobility of greater than 3.3 cm2V\xb7sec.
21. The device of claim 1, wherein the channel has an onoff ratio of greater than 1\xd7109.
22. A method of making an electronic device, the method comprising:
providing a substrate; and
forming a thin film transistor over the substrate, the thin film transistor comprising a channel, a gate electrode, an insulating layer, a source, and a drain, the insulating layer being interposed between the channel and the gate electrode, the source and drain contacting the channel,
wherein the channel comprises carbon nanotubes and an organic semiconductor material.
23. The method of claim 22, wherein the channel further comprises one or more materials selected from the group consisting of Au, Pt, Si, Ag, Fe, Ni, Co, and alloys comprising one or more of the foregoing elements.
24. The method of claim 22, wherein at least part of the carbon nanotubes are coated with one or more materials selected from the group consisting of Au, Pt, Si, Ag, Fe, Ni, Co, and alloys comprising one or more of the foregoing elements.
25. The method of claim 22, wherein the organic semiconductor material comprises one or more compounds selected from the group consisting of pentacene, oligo-thiophene, poly(alkyl-thiophene), and poly(thienylenevinylene).
26. The method of claim 22, forming the thin film transistor comprises:
forming the channel, which comprises forming a first layer and a second layer, wherein the first layer comprises the carbon nanotubes, and wherein the second layer comprises the organic semiconductor material and is substantially free of the carbon nanotubes.
27. The method of claim 22, wherein forming the thin film transistor comprises forming the channel, and wherein forming the channel comprises using one process selected from the group consisting of spin coating, ink-jet printing, and screen printing.
28. The method of claim 27, wherein forming the channel further comprises sintering at a temperature about 300\xb0 C. or lower.
29. The method of claim 26, wherein forming the second layer comprises using a method selected from the group consisting of vacuum deposition and organic vapor deposition.
30. The method of claim 26, wherein forming the second layer is at least partially performed in a vacuum atmosphere of 5\xd710\u22124 Torr or less.
31. A method of operating an electronic device, the method comprising:
providing the electronic device of claim 1; and
stimulating the electronic device to activate the channel of the thin film transistor,
wherein the channel has a charge mobility of greater than 3.3 cm2V\xb7sec during the activation.
32. The method of claim 31, wherein the channel has an onoff ratio of greater than 1\xd7109 during the activation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image forming apparatus comprising:
an input module, an output module, a process module, and a memory;
a packet switch having a plurality of ports and independent paths for data transmission, the packet switch being connected to the input, output and process modules, and to the memory; and
a path controlling part determining a process path based on data information from the input module and data transmission ability of paths within the image forming apparatus, and conducting a selection control to select a data transmission path in response to information stored in the memory, wherein the information includes data transmission delay time for each process path and a data type of data to be transmitted.
2. The image forming apparatus as claimed in claim 1, wherein information concerning the data transmission ability for each data type required between the input module and the output module is stored in the memory.
3. The image forming apparatus as claimed in claim 2, further comprising a delay measurement device, and wherein a value measured by said delay measurement device when power is on is stored in the memory as the information concerning the data transmission delay time.
4. The image forming apparatus as claimed in claim 2, wherein the information concerning the data transmission ability required between the input module and the output module at a minimum to store in the memory is updated each time a configuration of the image forming apparatus is changed.
5. The image forming apparatus as claimed in claim 1, wherein the memory stores path information, the information concerning the data transmission ability, and the information concerning the delay time when a path change is conducted.
6. The image forming apparatus of claim 3, further comprising a plotter unit, and wherein a sub-scan operation of said plotter unit is adjusted based on the delay time information stored in said memory.
7. The image forming apparatus of claim 1, wherein the data information used by the path controlling part are process state and used capacity of process module and memory.
8. The image forming apparatus of claim 1, wherein the packet switch is one of a plurality of packet switches of a packet switch network, each of the plurality of packet switches further comprising a plurality of selectors, and a plurality of switches.

1. An integrated circuit comprising a plurality of transistors that store a codeword determined by a difference in mobility between a first transistor and a further transistor of the plurality of transistors, wherein the plurality of transistors are arranged to form a bi-stable circuit having two stable states; and wherein the difference in mobility between the first transistor and the further transistor biases the bi-stable circuit towards one or the other of the stable states to determine the codeword.
2. The integrated circuit of claim 1, wherein the plurality of transistors comprise a first branch of series connected transistors comprising the first transistor, and a second branch of series connected transistors comprising the further transistor; wherein an output node of the first branch is connected to an input node of the second branch, and wherein an output node of the second branch is connected to an input node of the first branch, thereby forming the bi-stable circuit.
3. The integrated circuit of claim 1, comprising a plurality of the bi-stable circuits.
4. The integrated circuit of claim 1, wherein at least the first transistor has a width to length ratio of less than one.
5. The integrated circuit of claim 1, wherein at least the first transistor is located at a predetermined location of the die of the integrated circuit, the predetermined location being more susceptible to undergo physical stress than other areas of the die.
6. The integrated circuit of claim 5, wherein the predetermined location is at a corner or an edge of the die of the integrated circuit.
7. The integrated circuit of claim 1 wherein a stress layer (CAP) is provided to influence the stress within the transistors, thereby controlling the mobilities of the transistors and hence the value of the codeword.
8. The integrated circuit of claim 7, wherein the stress layer comprises a compressive stress layer and a tensile stress layer, the compressive stress layer setting a first level of mobility and the tensile stress layer setting a second level of mobility.
9. Apparatus comprising the integrated circuit of claim 1 and a reader for connecting to the integrated circuit and reading the codeword, the reader comprising a driver for driving the integrated circuit to determine the codeword.
10. A method for reading a codeword stored in an integrated circuit according to claim 1, the method comprising driving the integrated circuit to determine a codeword, the codeword being determined by the difference in mobility between the first transistor and a further transistor of a bi-stable circuit of the integrated circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A dynamic voltage scaling system based on on-chip monitoring and voltage prediction, comprising:
a main circuit that has integrated on-chip monitoring circuits,
a supply voltage scaling module, and
a voltage converter connected to an output terminal of the supply voltage scaling module, with an output terminal of the voltage converter connected to an input terminal of the main circuit, wherein, the supply voltage scaling module comprises
a state transition probability generation module and an error prediction module designed according to the main circuit, and a sampling and statistics module and a state recording module connected in sequence to the output terminals of the on-chip monitoring circuits, the output terminals of the state recording module and state transition probability generation module are connected to the input terminals of the error prediction module; wherein the on-chip monitoring circuits create monitored error signals and sends the monitored error signals to the sampling and statistics module which calculates the error rate of the main circuit in the current time slice, and outputs to the state recording module, and the state recording module records the error rate and the corresponding supply voltage; the error prediction module utilizes the Markov theory to predict the error rate of the main circuit in a future time slice according to the probability generated by the state recording module and the state transition probability generation module, and generate regulation signals to control the output voltage of the voltage converter.
2. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 1, wherein, the state transition probability generation module employs a state transition probability look-up table.
3. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 2, wherein, the state transition probability look-up table is created as follows: after the main circuit is designed completely, the main circuit is subjected to run a large-size program at different voltages, and perform statistics in a large quantity, to obtain the state transition probability of the main circuit from the current state skip to the next state at different voltages, and store in the form of a look-up table.
4. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 1, wherein, the processing procedure of the sampling and statistics module comprises the following steps: first, dividing the operation time of the main circuit into N time slices in equal size; next, performing statistics on the total number of error signals Nerror in the main circuit sent from the on-chip monitoring circuits in n\u22121th time slice; finally, calculating the error rate Rerror of the main circuit in the n\u22121th time slice: Rerror=NerrorNtotal, where, Ntotal is the total number of sampled signals of the main circuit in the n\u22121th time slice; wherein, 2\u2266n\u2266N\u22121, N\u22673, and both N and n are integral number.
5. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 4, wherein, the length of the time slice is not shorter than the maximum duration required for performing voltage scaling once by the voltage converter.