Author: claimsbot

What is claimed is:

1. A decoder that is operable to decode a Low Density Parity Check (LDPC) coded signal, the decoder comprising:
a Sum-Product (SP) soft decision decoder that performs a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
wherein the SP soft decision decoder generates a first plurality of hard decisions using the plurality of soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations; and
a Bit-Flip (BF) hard decision decoder that performs a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder to generate a second plurality of hard decisions.
2. The decoder of claim 1, wherein the plurality of soft decision decoding iterations performed by the SP soft decision decoder is a predetermined number of soft decision decoding iterations.
3. The decoder of claim 1, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed by the SP soft decision decoder when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
4. The decoder of claim 1, wherein the plurality of hard decision decoding iterations performed by the BF hard decision decoder is a predetermined number of hard decision decoding iterations.
5. The decoder of claim 1, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed by the BF hard decision decoder when a number of bit errors within the plurality of hard decisions is less than a predetermined threshold.
6. The decoder of claim 1, wherein the SP soft decision decoder performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoder performs not more than 2 hard decision decoding iterations.
7. The decoder of claim 1, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
8. The decoder of claim 1, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
9. The decoder of claim 1, further comprising a syndrome error detection functional block that is operable to detect a bit error within the second plurality of hard decisions after the BF hard decision decoder performs the plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder.
10. The decoder of claim 9, wherein the SP soft decision decoder performs an additional plurality of soft decision decoding iterations when the syndrome error detection functional block detects the bit error within the second plurality of hard decisions.
11. The decoder of claim 10, wherein the BF hard decision decoder outputs a hard decision decoding result when the SP soft decision decoder fails to eliminate the bit error after performing the additional plurality of soft decision decoding iterations; and
wherein the hard decision decoding result output from the BF hard decision decoder includes an estimated codeword of the LDPC coded signal.
12. The decoder of claim 10, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
13. The decoder of claim 10, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
14. The decoder of claim 1, wherein the SP soft decision decoder performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
15. The decoder of claim 1, wherein the decoder is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.
16. A decoder that is operable to decode a Low Density Parity Check (LDPC) coded signal, the decoder comprising:
a Sum-Product (SP) soft decision decoder that performs a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
wherein the SP soft decision decoder performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations;
wherein the SP soft decision decoder generates a first plurality of hard decisions using the plurality of soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations;
a Bit-Flip (BF) hard decision decoder that performs a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder to generate a second plurality of hard decisions;
a syndrome error detection functional block that is operable to detect a bit error within the second plurality of hard decisions after the BF hard decision decoder performs the plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder; and
wherein the SP soft decision decoder performs an additional plurality of soft decision decoding iterations when the syndrome error detection functional block detects the bit error within the second plurality of hard decisions.
17. The decoder of claim 16, wherein the plurality of soft decision decoding iterations performed by the SP soft decision decoder is a predetermined number of soft decision decoding iterations.
18. The decoder of claim 16, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed by the SP soft decision decoder when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
19. The decoder of claim 16, wherein the plurality of hard decision decoding iterations performed by the BF hard decision decoder is a predetermined plurality of hard decision decoding iterations.
20. The decoder of claim 16, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed by the BF hard decision decoder when a number of bit errors within the plurality of hard decisions is less than a predetermined threshold.
21. The decoder of claim 16, wherein the SP soft decision decoder performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoder performs not more than 2 hard decision decoding iterations.
22. The decoder of claim 16, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
23. The decoder of claim 16, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
24. The decoder of claim 16, wherein the BF hard decision decoder outputs a hard decision decoding result when the SP soft decision decoder fails to eliminate the bit error after performing the additional plurality of soft decision decoding iterations; and
wherein the hard decision decoding result output from the BF hard decision decoder includes an estimated codeword of the LDPC coded signal.
25. The decoder of claim 16, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
26. The decoder of claim 16, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
27. The decoder of claim 16, wherein the SP soft decision decoder performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
28. The decoder of claim 16, wherein the decoder is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.
29. A decoder that is operable to decode a Low Density Parity Check (LDPC) coded signal, the decoder comprising:
a Sum-Product (SP) soft decision decoder that performs a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
wherein the SP soft decision decoder generates a first plurality of hard decisions using the plurality of soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations;
a Bit-Flip (BF) hard decision decoder that performs a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder to generate a second plurality of hard decisions;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
30. The decoder of claim 29, wherein the plurality of soft decision decoding iterations performed by the SP soft decision decoder is a predetermined number of soft decision decoding iterations.
31. The decoder of claim 29, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed by the SP soft decision decoder when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
32. The decoder of claim 29, wherein the plurality of hard decision decoding iterations performed by the BF hard decision decoder is a predetermined number of hard decision decoding iterations.
33. The decoder of claim 29, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed by the BF hard decision decoder when a number of bit errors within the plurality of hard decisions is less than a predetermined threshold.
34. The decoder of claim 29, wherein the SP soft decision decoder performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoder performs not more than 2 hard decision decoding iterations.
35. The decoder of claim 29, further comprising a syndrome error detection functional block that is operable to detect a bit error within the second plurality of hard decisions after the BF hard decision decoder performs the plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder.
36. The decoder of claim 35, wherein the SP soft decision decoder performs an additional plurality of soft decision decoding iterations when the syndrome error detection functional block detects the bit error within the second plurality of hard decisions.
37. The decoder of claim 36, wherein the BF hard decision decoder outputs a hard decision decoding result when the SP soft decision decoder fails to eliminate the bit error after performing the additional plurality of soft decision decoding iterations; and
wherein the hard decision decoding result output from the BF hard decision decoder includes an estimated codeword of the LDPC coded signal.
38. The decoder of claim 36, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
39. The decoder of claim 36, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
40. The decoder of claim 29, wherein the SP soft decision decoder performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
41. The decoder of claim 29, wherein the decoder is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.
42. A decoder that is operable to decode a Low Density Parity Check (LDPC) coded signal, the decoder comprising:
a Sum-Product (SP) soft decision decoder that performs a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
wherein the SP soft decision decoder generates a first plurality of hard decisions using the plurality of soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations;
a Bit-Flip (BF) hard decision decoder that performs a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder to generate a second plurality of hard decisions;
wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
43. The decoder of claim 42, wherein the plurality of soft decision decoding iterations performed by the SP soft decision decoder is a predetermined number of soft decision decoding iterations.
44. The decoder of claim 42, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed by the SP soft decision decoder when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
45. The decoder of claim 42, wherein the plurality of hard decision decoding iterations performed by the BF hard decision decoder is a predetermined number of hard decision decoding iterations.
46. The decoder of claim 42, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed by the BF hard decision decoder when a number of bit errors within the plurality of hard decisions is less than a predetermined threshold.
47. The decoder of claim 42, wherein the SP soft decision decoder performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoder performs not more than 2 hard decision decoding iterations.
48. The decoder of claim 42, further comprising a syndrome error detection functional block that is operable to detect a bit error within the second plurality of hard decisions after the BF hard decision decoder performs the plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoder.
49. The decoder of claim 48, wherein the SP soft decision decoder performs an additional plurality of soft decision decoding iterations when the syndrome error detection functional block detects the bit error within the second plurality of hard decisions.
50. The decoder of claim 49, wherein the BF hard decision decoder outputs a hard decision decoding result when the SP soft decision decoder fails to eliminate the bit error after performing the additional plurality of soft decision decoding iterations; and
wherein the hard decision decoding result output from the BF hard decision decoder includes an estimated codeword of the LDPC coded signal.
51. The decoder of claim 49, wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
52. The decoder of claim 49, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
wherein metrics within the plurality of metrics are selectively scaled, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
wherein information corresponding to a plurality of variable nodes is initialized using hard decisions generated from the plurality of scaled metrics; and
wherein the initialized information corresponding to the plurality of variable nodes is used by the SP soft decision decoder before performing a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
53. The decoder of claim 42, wherein the SP soft decision decoder performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
54. The decoder of claim 42, wherein the decoder is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.
55. A method that decodes a Low Density Parity Check (LDPC) coded signal, the method comprising:
Sum-Product (SP) soft decision decoding to perform a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
generating a first plurality of hard decisions using the soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations; and
Bit-Flip (BF) hard decision decoding to perform a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoding to generate a second plurality of hard decisions.
56. The method of claim 55, wherein the plurality of soft decision decoding iterations is a predetermined number of soft decision decoding iterations.
57. The method of claim 55, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
58. The method of claim 55, wherein the plurality of hard decision decoding iterations is a predetermined number of hard decision decoding iterations.
59. The method of claim 55, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed when a number of bit errors within the second plurality of hard decisions is less than a predetermined threshold.
60. The method of claim 55, wherein the SP soft decision decoding performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoding performs not more than 2 hard decision decoding iterations.
61. The method of claim 55, further comprising:
initializing information corresponding to a plurality of variable nodes using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
62. The method of claim 55, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
further comprising:
selectively scaling the plurality of metrics, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
generating hard decisions from the plurality of scaled metrics;
initializing information corresponding to a plurality of variable nodes using the hard decisions generated from the plurality of scaled metrics; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
63. The method of claim 55, further comprising:
detecting a bit error within the second plurality of hard decisions after the plurality of hard decision decoding iterations is made on the first plurality of hard decisions generated during the at least one soft decision decoding iteration of the plurality of soft decision decoding iterations.
64. The method of claim 63, further comprising:
performing an additional plurality of soft decision decoding iterations when a bit error has been detected within the second plurality of hard decisions.
65. The method of claim 64, further comprising:
outputting a hard decision decoding result when the additional plurality of soft decision decoding iterations fails to eliminate the bit error; and
wherein the hard decision decoding result output includes an estimated codeword of the LDPC coded signal.
66. The method of claim 64, further comprising:
initializing information corresponding to a plurality of variable nodes using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
67. The method of claim 64, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
further comprising:
selectively scaling the plurality of metrics, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
generating hard decisions from the plurality of scaled metrics;
initializing information corresponding to a plurality of variable nodes using the hard decisions generated from the plurality of scaled metrics; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
68. The method of claim 55, wherein the SP soft decision decoding involves performing momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
69. The method of claim 55, wherein the method is performed within a decoder that is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.
70. A method that decodes a Low Density Parity Check (LDPC) coded signal, the method comprising:
Sum-Product (SP) soft decision decoding to perform a plurality of soft decision decoding iterations to generate a plurality of soft decisions corresponding to bits within the LDPC coded signal;
wherein the SP soft decision decoding performs momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations;
generating a first plurality of hard decisions using the soft decisions generated during at least one soft decision decoding iteration of the plurality of soft decision decoding iterations;
Bit-Flip (BF) hard decision decoding to perform a plurality of hard decision decoding iterations on the first plurality of hard decisions generated by the SP soft decision decoding to generate a second plurality of hard decisions;
detecting a bit error within the second plurality of hard decisions after the plurality of hard decision decoding iterations is made on the first plurality of hard decisions generated during the at least one soft decision decoding iteration of the plurality of soft decision decoding iterations; and
additional SP soft decision decoding to perform an additional plurality of soft decision decoding iterations when a bit error has been detected within the second plurality of hard decisions.
71. The method of claim 70, wherein the plurality of soft decision decoding iterations is a predetermined number of soft decision decoding iterations.
72. The method of claim 70, wherein the at least one soft decision decoding iteration is a last soft decision decoding iteration of the plurality of soft decision decoding iterations that is performed when a number of bit errors within the plurality of soft decisions is less than a predetermined threshold.
73. The method of claim 70, wherein the plurality of hard decision decoding iterations is a predetermined number of hard decision decoding iterations.
74. The method of claim 70, wherein a last hard decision decoding iteration of the plurality of hard decision decoding iterations is performed when a number of bit errors within the plurality of hard decisions is less than a predetermined threshold.
75. The method of claim 70, wherein the SP soft decision decoding performs not more that 6 soft decision decoding iterations; and
wherein the BF hard decision decoding performs not more than 2 hard decision decoding iterations.
76. The method of claim 70, further comprising:
initializing information corresponding to a plurality of variable nodes using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
77. The method of claim 70, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
further comprising:
selectively scaling the plurality of metrics, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
generating hard decisions from the plurality of scaled metrics;
initializing information corresponding to a plurality of variable nodes using the hard decisions generated from the plurality of scaled metrics; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the plurality of soft decision decoding iterations.
78. The method of claim 70, further comprising:
outputting a hard decision decoding result when the additional plurality of soft decision decoding iterations fails to eliminate the bit error; and
wherein the hard decision decoding result output includes an estimated codeword of the LDPC coded signal.
79. The method of claim 70, further comprising:
initializing information corresponding to a plurality of variable nodes using hard decisions generated from a plurality of metrics that is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
80. The method of claim 70, wherein a plurality of metrics is based on a plurality of received symbols within the LDPC coded signal and channel information corresponding to a communication channel over which the LDPC coded signal has been communicated;
further comprising:
selectively scaling the plurality of metrics, based on a Signal to Noise Ratio (SNR) of the communication channel, to generate a plurality of scaled metrics;
generating hard decisions from the plurality of scaled metrics;
initializing information corresponding to a plurality of variable nodes using the hard decisions generated from the plurality of scaled metrics; and
using the initialized information corresponding to the plurality of variable nodes to initialize a first soft decision decoding iteration of the additional plurality of soft decision decoding iterations.
81. The method of claim 70, wherein the SP soft decision decoding involves performing momentum modified SP soft decision decoding processing that involves updating the plurality of soft decisions using information corresponding to 2 previous soft decision decoding iterations of the plurality of soft decision decoding iterations.
82. The method of claim 70, wherein the method is performed within a decoder that is implemented within a communication receiver; and
the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An optical component adapted for attachment to an optical bench, the optical component comprises an alignment feature for positioning the optical component relative to the optical bench, wherein the alignment feature extends into the optical component from an exterior wall, the alignment feature comprising a reentrant sidewall.
2. An optical component as claimed in claim 1, wherein the alignment feature is formed in a bottom face of the optical component.
3. An optical component as claimed in claim 1, wherein a proximal origin of the reentrant sidewall is depressed relative to the exterior wall surrounding the alignment feature.
4. An optical component as claimed in claim 3, wherein the outer exterior wall is bonded to the optical bench.
5. An optical component as claimed in claim 1, wherein the exterior wall surrounding the alignment feature is bonded to the optical bench.
6. An optical component as claimed in claim 1, wherein the exterior wall is depressed relative a surface that is bonded to the optical bench.
7. An optical component as claimed in claim 1, wherein the alignment feature comprises a slot that extends along a length of the optical component.
8. An optical component as claimed in claim 1, wherein the alignment feature comprises a slot that extends along an entire length of the optical component.
9. An optical component as claimed in claim 1, further comprising a coating over the optical component that is used to attach the optical component to the optical bench.
10. An optical component as claimed in claim 9, wherein the coating is between 0.5 and 10 micrometers thick.
11. An optical component as claimed in claim 9, wherein the coating is about 3 micrometers thick.
12. An optical component as claimed in claim 9, wherein the coating is plated on the optical component.
13. An optical component as claimed in claim 9, wherein the coating is sputtered on the optical component.
14. An optical component as claimed in claim 1, further comprising a gold plated layer on the optical component over the alignment feature.
15. An optical component as claimed in claim 1, further comprising multiple alignment features spaced from each other along a width of the optical component.
16. An optical component as claimed in claim 15, further comprising at least two of the alignment features having different widths with respect to each other.
17. An optical component as claimed in claim 1, wherein a waist of the alignment feature is between 10 and 100 micrometers wide.
18. An optical component as claimed in claim 1, wherein a waist of the alignment feature is between 10 and 50 micrometers wide.
19. An optical component as claimed in claim 1, wherein a waist of the alignment feature is about 25 micrometers wide.
20. An optical component as claimed in claim 1, wherein a waist of the alignment feature is about 50 micrometers wide.
21. An optical component as claimed in claim 1, further comprising a gold alloy coating on the optical component over the alignment feature for attaching the optical component to the optical bench.
22. An optical component adapted for precision attachment to an optical bench, the optical component comprising an alignment feature for positioning the optical component relative to the optical bench, wherein the alignment feature extends into the optical component from an exterior wall, the alignment feature comprising two opposed reentrant sidewalls.
23. An optical component as claimed in claim 22, wherein the alignment feature has a frusto-triangular profile.
24. An optical component as claimed in claim 23, wherein a waist of the alignment feature is between 10 and 100 micrometers wide.
25. An optical component as claimed in claim 23, wherein a waist of the alignment feature is between 10 and 50 micrometers wide.
26. An optical component as claimed in claim 22, wherein the alignment feature has an hourglass profile.
27. An optical component as claimed in claim 26, wherein a waist of the alignment feature is between 10 and 100 micrometers wide.
28. An optical component as claimed in claim 26, wherein a waist of the alignment feature is between 10 and 50 micrometers wide.
29. A method for installing an optical component (100) on an optical bench (10), the method comprising:
determining a position of the optical component (100) by reference to an alignment feature (310) formed into an exterior wall (210) of the optical component;
determining a position of the optical bench (10) by reference to a bench alignment feature (22); and
bonding the optical component (100) to the optical bench (10).
30. A method as claimed in claim 29, wherein the step of determining the position of the optical component (100) includes locating a proximal origin (328) of a sidewall (320).
31. A method as claimed in any one of the claims 29, wherein the step of bonding comprises solder bonding the optical component (100) to the optical bench (10).

1. A system for investigating non-linear properties of a rock formation around a borehole, comprising:
a first sub-system configured to perform data acquisition, control and recording of data;
a second subsystem in communication with the first sub-system and configured to perform non-linearity and velocity preliminary imaging;
a third subsystem in communication with the first subsystem and configured to emit controlled acoustic broadcasts and receive acoustic energy;
a fourth subsystem in communication with the first subsystem and the third subsystem and configured to generate a source signal directed towards the rock formation; and
a fifth subsystem in communication with the third subsystem and the fourth subsystem and configured to perform detection of signals representative of the non-linear properties of the rock formation, the fifth subsystem comprising a template signal generator module configured to generate a template signal designed according to forecast properties of the signals to be detected.
2. The system according to claim 1, wherein the first subsystem comprises an acquisition modeling module configured to receive inputs from the second subsystem and operator inputs.
3. The system according to claim 2, wherein the first subsystem comprises a data acquisition controller configured to receive operator inputs and inputs from an acquisition design module.
4. The system according to claim 3, wherein the first subsystem comprises a data pre-processing and enhancement module and a data storage device, the data pre-processing and enhancement module configured to read data from the data storage device and input data into the second subsystem.
5. The system according to claim 1, wherein the second subsystem comprises an initial velocity model module configured to provide an initial velocity model derived from logs of compressional and shear slowness and information about formation lateral continuity to the first subsystem.
6. The system according to claim 5, wherein the second subsystem comprises an image initializing module configured to initialize volumes of propagation compressional and shear velocity values, velocity ratio images and images of non-linearity which are associated with amplitudes of a measured signal generated by the non-linear interaction at a mixing zone.
7. The system according to claim 1, wherein the third subsystem comprises a first acoustic source, a second acoustic source, one or more receivers, a tool deployment and transport module, a tool mechanical controller, a directional controller for controlling an orientation of the first acoustic signal, and a directional controller for controlling an orientation of the second acoustic signal.
8. The system according to claim 7, wherein the third system is configured to receive from the first subsystem commands to control the directional controllers within the third subsystem to control azimuth and elevation angles of the first acoustic signal, the second acoustic signal, or both.
9. The system according to claim 7, wherein acquisition record parameters pertaining to tool configuration and broadcast geometry are collected from the third subsystem and are recorded in a data storage device within the first subsystem.
10. The system according to claim 1, wherein the fourth subsystem comprises a signal generator configured to generate a first signal, a signal generator configured to generate a second acoustic signal, a frequency multiplier and start time difference module, and a coded signal generator.
11. The system according to claim 10, wherein the fourth subsystem is configured to receive input commands from the first subsystem.
12. The system according to claim 11, wherein the fourth subsystem is configured to receive input commands from the first subsystem so as to generate pulse sequences using the coded signal generator module.
13. The system according to claim 12, wherein the coded signal generated by the coded signal generator module is input into a first signal control and amplifier module to input a first signal at a first frequency to the first acoustic source, wherein the coded signal generated by the coded signal generator module is input into frequency multiplier and start time difference module and then input into a second signal control and amplifier module to provide a second signal to the second acoustic source having a start time difference relative to the first signal and having a second frequency which is a selected fraction of the first frequency.
14. The system according to claim 13, wherein the start time difference and the frequency fraction and are stored as record broadcast information in a data storage device within the first sub-system.
15. The system according to claim 1, wherein the fifth subsystem comprises a receiver module configured to receive a signal from one or more receivers, a non-linear signal enhancement module configured to enhance the signal received by the signal receiver module, and a signal correlation module configured to correlate the received signal with the template signal.
16. The system according to claim 15, wherein signals from the receiver module are processed by the non-linear signal enhancement module to enhance a content of non-linear origin and reduce noise, wherein the signals from the receiver module and enhanced signals are stored in a data storage device within the first sub-system.
17. The system according to claim 15, wherein the correlation module is configured to correlate the template signal with the received signal so as to extract a correlated signal, the correlated signal identifying a signal generated at an intersection of a first signal from a first acoustic source and a second signal from a second acoustic in a non-linear mixing zone within the rock formation around the borehole.
18. The system according to claim 17, wherein the correlated signal is stored in a data storage device within the first subsystem.
19. The system according to claim 18, wherein a data acquisition controller within the first subsystem is configured to repeat recording within the storage device of the first subsystem and repeat extracting the correlated data from a plurality of values of the position of the first acoustic source, the position of the second acoustic source, the position of the receiver, an elevation angle of the first acoustic signal, or an elevation angle of the second acoustic signal, or any combination of two or more thereof.
20. The system according to claim 19, further comprising a hodogram analysis module configured to process stored data within the storage device to further enhance the correlated data.
21. The system according to claim 1, further comprising a sixth subsystem in communication with the second subsystem and configured to perform imaging of non-linear properties of the rock formation and determining acoustic signal velocity within the rock formation.
22. The system according to claim 21, wherein the sixth subsystem comprises sub-system a data pre-processing and enhancement module, a velocity model iteration module, an imaging iteration module, an output image module for velocity ratio images andor non-linearity images, and an output velocity module for outputting determined values of compressional velocity Vp, shear velocity Vs, or velocity ratio between the compressional velocity and the shear velocity, or any combination of two or more thereof.
23. The system according to claim 17, wherein the correlated signal is a function of signal time t, frequency ratio d of a first frequency of the first signal and a second frequency of the second signal, and a time delay \u03b4 between the first signal and the second signal.
24. The system according to claim 1, wherein the fifth subsystem further comprises a signal correlation module configured to correlate detected signals with the template signal to extract a correlated signal representative of an acoustic signal generated by a nonlinear interaction of the controlled acoustic broadcasts in a non-linear mixing zone within the rock formation around the borehole.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An apparatus comprising:
a phase recoverer to approximately match a phase of a clock signal to a phase of a first signal, wherein the phase recoverer outputs samples of the first signal;
a storage device to store samples based upon the phase adjusted clock signal; and
a clock multiplication unit to provide the clock signal to the phase recoverer and to transfer samples from the storage device.
2. The apparatus of claim 1, wherein the phase recoverer comprises:
a detector to compare a phase of the first signal with a phase of the clock signal and to output a comparison; and
a phase matcher to approximately match the phase of the clock signal with the phase of the first signal based upon the comparison.
3. The apparatus of claim 2, wherein the detector comprises an Alexander type phase detector.
4. The apparatus of claim 1, wherein the storage device is to indicate an overflow state.
5. The apparatus of claim 1, wherein the storage device is to indicate an underflow state.
6. The apparatus of claim 1, wherein the clock multiplication unit is to generate the clock signal based upon a second clock signal.
7. An apparatus comprising:
a clock signal source to provide a clock signal and a first signal, wherein the first signal and clock signal include similar amounts of jitter;
a phase recoverer to approximately match a phase of the clock signal to a phase of the first signal, wherein the phase recoverer outputs samples of the first signal;
a storage device to store samples based upon the phase adjusted clock signal; and
a clock multiplication unit to transfer samples from the storage device.
8. The apparatus of claim 7, wherein the phase recoverer comprises:
a detector to compare a phase of the first signal with a phase of the clock signal and output a comparison; and
a delay locked loop to approximately match the phase of the clock signal with the phase of the first signal based upon the comparison.
9. The apparatus of claim 8, wherein the detector comprises an Alexander type phase detector.
10. The apparatus of claim 7, wherein the storage device is to indicate an overflow state.
11. The apparatus of claim 7, wherein the storage device is to indicate an underflow state.
12. The apparatus of claim 7, wherein the clock multiplication unit is to transfer samples based upon a second clock signal.
13. The apparatus of claim 7, further comprising an output device to receive samples from the clock multiplication unit, wherein the output device comprises:
a driver to amplify samples; and
an electrical-to-optical converter to convert the samples into optical format.
14. The apparatus of claim 7, wherein the clock signal source comprises logic to perform forward error correction on the first signal.
15. The apparatus of claim 7, wherein the clock signal source comprises logic to perform media access control on the first signal in compliance with Ethernet.
16. The apparatus of claim 7, wherein the clock signal source comprises logic to perform framing and wrapping on the first signal in compliance with ITU-T G.709.
17. A system comprising:
an input device to provide a first signal;
a phase recoverer to approximately match a phase of a clock signal to a phase of the first signal, wherein the phase recoverer outputs samples of the first signal;
a storage device to store samples based upon the phase adjusted clock signal;
a clock multiplication unit to provide the clock signal to the phase recoverer and to transfer samples from the storage device; and
an output device to receive samples from the clock multiplication unit.
18. The system of claim 17, wherein the input device comprises logic to perform forward error correction on the first signal.
19. The system of claim 17, wherein the input device comprises logic to perform media access control on the first signal in compliance with Ethernet.
20. The system of claim 17, wherein the input device comprises logic to perform framing and wrapping on the first signal in compliance with ITU-T G.709.
21. The system of claim 17, wherein the output device comprises:
a driver to amplify the samples; and
an electrical-to-optical converter to convert the samples into optical format.
22. An apparatus comprising:
a phase recoverer comprising a first single side band voltage controlled oscillator to provide a first clock signal, wherein the phase recoverer is to approximately match a phase of the first clock signal to a phase of a first signal and wherein the phase recoverer outputs samples of the first signal;
a storage device to store samples based upon the phase adjusted first clock signal; and
a clock multiplication unit comprising a second single side band voltage controlled oscillator to generate a second clock signal, wherein the first and second single side band voltage controlled oscillators operate at different center frequencies and wherein the clock multiplication unit is to transfer samples from the storage device based upon the second clock signal.
23. The apparatus of claim 22, further comprising an input device, wherein the input device comprises logic to perform forward error correction on the first signal.
24. The apparatus of claim 22, further comprising an input device, wherein the input device comprises logic to perform media access control on the first signal in compliance with Ethernet.
25. The apparatus of claim 22, further comprising an input device, wherein the input device comprises logic to perform framing and wrapping on the first signal in compliance with ITU-T G.709.
26. The apparatus of claim 22 further comprising an output device to receive samples from the clock multiplication unit:
a driver to amplify the samples; and
an electrical-to-optical converter to convert the samples into optical format.
27. The apparatus of claim 22, wherein the clock multiplication unit is to generate the second clock signal based upon a reference clock signal.
28. A method comprising:
matching a phase of a clock signal to a phase of an input signal;
recording samples of the input signal based upon the phase matched clock signal; and
transferring samples of the input signal based upon the clock signal.
29. The method of claim 28, further comprising:
indicating an overflow state when the recorded samples exceed a threshold.
30. The method of claim 28, further comprising:
indicating an underflow state when the recorded samples exceed a threshold.
31. A method comprising the acts of:
matching a phase of a clock signal to a phase of an input signal, wherein the clock signal and input signal include similar amounts of jitter;
recording samples of the input signal based upon the phase matched clock signal; and
transferring samples of the input signal based upon the clock signal.
32. The method of claim 31, further comprising:
indicating an overflow state when the recorded samples exceed a threshold.
33. The method of claim 31, further comprising:
indicating an underflow state when the recorded samples exceed a threshold.
34. A method comprising:
matching a phase of a first clock signal to a phase of an input signal;
recording samples of the input signal based upon the phase matched first clock signal; and
transferring samples of the input signal based upon a second clock signal, wherein the first and second clock signals are based on clock signals from separate single side band voltage controlled oscillators operating at different frequencies.
35. The method of claim 34, further comprising:
indicating an overflow state when the recorded samples exceed a threshold.
36. The method of claim 34, further comprising:
indicating an underflow state when the recorded samples exceed a threshold.