1. Illumination device for dark-field illumination for an optical testing device for scanning an object, such as e.g. a wafer, a mirror or a glass plate, with a light source for dark-field illumination and a reflector, wherein the reflector has in cross-section the form of a segment of an ellipse, and the illumination device may be arranged with a first focal point (F1) of the ellipse on the surface of the object, and the light source is located at a point which results from reflection of the second focal point (F2) of the ellipse on the surface of the object.
2. Illumination device according to claim 1,
wherein the reflector is in the form of an elongated channel for scanning a line on an object.
3. Illumination device according to claim 2,
wherein the light source for dark-field illumination is located at the apex of the reflector.
4. Illumination device according to claim 3,
wherein there is provided a light source for bright-field illumination which is offset relative to the light source for dark-field illumination.
5. Illumination device according to claim 1,
wherein the reflector is in the form of a segment of an ellipsoid.
6. Illumination device according to claim 5,
wherein the light source for dark-field illumination is located at the apex of the reflector.
7. Illumination device according to claim 1,
wherein the light source for dark-field illumination is located at the apex of the reflector.
8. Illumination device according to claim 1,
wherein there is provided a light source for bright-field illumination which is offset relative to the light source for dark-field illumination.
9. Illumination device according to claim 8,
characterised in that the light source for dark-field illumination and the light source for bright-field illumination emit light of different color.
10. Illumination device according to claim 8,
wherein the light source for bright-field illumination is deigned to produce a light beam bundle, directed on to the first focal point (F1).
11. Illumination device according to claim 10,
wherein the light source for dark-field illumination and the light source for bright-field illumination emit light of different color.
12. Illumination device according to claim 1,
wherein there is provided a single light source which emits white light, and at least one color filter is arranged so that light which is reflected for instance from one area of the reflector serving for bright-field illumination has a different color from the rest of the light.
13. Illumination device according to claim 6,
wherein there is provided a single light source which emits white light, and at least one color filter is arranged so that light which is reflected for instance from one area of the reflector serving for bright-field illumination has a different color from the rest of the light.
14. Illumination device according to claim 1,
wherein there is provided a single light source which emits blue light, and the reflector is coated in a predetermined area with a coating which converts the light into longer-wave light, wherein the predetermined area of the reflector is the area used for bright-field illumination.
15. Illumination device according to claim 6,
wherein there is provided a single light source which emits blue light, and the reflector is coated in a predetermined area with a coating which converts the light into longer-wave light, wherein the predetermined area of the reflector is the area used for bright-field illumination.
16. Illumination device according to claim 1,
wherein the light source has one or several light-emitting diodes.
17. Illumination device according to claim 11,
wherein the light source has one or several light-emitting diodes.
18. Illumination device according to claim 15,
wherein the light source has one or several light-emitting diodes.
19. Illumination device according to claim 1,
wherein there is provided an optical sensor, preferably located in the light beam bundle of the light source for bright-field illumination reflected at the object.
20. Illumination device according to claim 17,
wherein there is provided an optical sensor, preferably located in the light beam bundle of the light source for bright-field illumination reflected at the object.
21. Illumination device according to claim 18,
wherein there is provided an optical sensor, preferably located in the light beam bundle of the light source for bright-field illumination reflected at the object.
22. Illumination device according to claim 19,
wherein the reflector has an optical aperture for the exit of a light beam bundle, which is directed on to the optical sensor.
23. Illumination device according to claim 20,
wherein the reflector has an optical aperture for the exit of a light beam bundle, which is directed on to the optical sensor.
24. Illumination device according to claim 21,
wherein the reflector has an optical aperture for the exit of a light beam bundle, which is directed on to the optical sensor.
25. Illumination device according to claim 1,
wherein the reflector is provided with matt areas in order to limit the angular range of the dark-field illumination.
26. Illumination device according to claim 2,
wherein the reflector is provided with matt areas in order to limit the angular range of the dark-field illumination.
27. Testing device for scanning the surface of an object, such as e.g. a wafer, a mirror or a glass plate, comprising
an illumination device according to claim 1, and
a slide unit for moving the illumination device relative to the object, and
an evaluation unit for producing an image of the surface of the object with the aid of the relative position between the reflector and the object and the respective image data detected by the sensor.
28. Method for the optical scanning of objects,
wherein an illumination device for dark-field illumination for an optical testing device for scanning an object, such as e.g. a wafer, a mirror or a glass plate, with a light source for dark-field illumination and a reflector is used, wherein the reflector has in cross-section the form of a segment of an ellipse, and the illumination device may be arranged with a first focal point (F1) of the ellipse on the surface of the object, and the light source is located at a point which results from reflection of the second focal point (F2) of the ellipse on the surface of the object, in order to scan the surface of an object, in particular a wafer, a mirror, a glass plate or a printed circuit board.
29. Method according to claim 28,
wherein the illumination device is held with the first focal point (F1) for instance on the surface of the objective to be scanned, and
the illumination device is moved relative to the object.
30. Illumination device for dark-field illumination in an optical testing device for scanning an object, the illumination device comprising:
a light source; and
a reflector,
wherein the reflector has an elliptical curvature with a first focal point and a second focal point, the object being located relative to the first focal point and the light source being located relative to a point resulting from reflection of the second focal point on the surface of the object.
31. Illumination device according to claim 30,
wherein the reflector is in the form of an elongated channel for scanning a line on an object.
32. Illumination device according to claim 30,
wherein the light source for dark-field illumination is located at an apex of the reflector.
33. Illumination device according to claim 30, further comprising:
a light source for bright-field illumination which is offset relative to the light source for dark-field illumination.
34. Illumination device according to claim 30,
wherein the reflector is in the form of a segment of an ellipsoid.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a target design; and
modifying the target design to create an altered target design database in response to the results of the space checks, wherein modifying the target design includes a first movement of a group of at least one edge on a feature within the target design to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed, and wherein modifying the target design further includes a second movement of a group of at least one edge on a feature to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed in response to the first movement of edges, wherein the first movement includes moving predetermined feature edges by moving edges of routing poly outward and interacting routing poly inward.
2. The method of claim 1, wherein modifying the target design includes utilizing at least one of design rule checking (DRC), rule-based optical proximity correction (RB-OPC) and model-based optical proximity correction (MB-OPC) software functions to perform one or more of the first movement and the second movement.
3. The method of claim 1, wherein the first movement includes moving predetermined feature edges by use of prioritization of the feature edges to be moved based upon at least one of electrical yield information and patterning process control capability.
4. The method of claim 1, wherein the first movement includes moving predetermined feature edges by shifting edges of vias and shifting edges of interacting metal features.
5. The method of claim 1, wherein the first movement includes moving predetermined feature edges by optimization of the distance which feature edges are moved based upon mask error factor (MEF) information.
6. The method of claim 1, wherein the first movement includes moving predetermined feature edges by shifting an edge of an interconnect feature with space less than a predetermined value to another non-electrically connected interconnect feature on the same layer in order to decrease the risk of feature merging and without reducing interconnect enclosure of via or contact features.
7. The method of claim 6, wherein shifting nearby edges of non-electrically connected interconnect features away from the other feature includes the shifting of via or contact features to prevent reduction in the interconnect enclosure of via or contact features.
8. The method of claim 1, wherein the first movement further includes moving predetermined feature edges by the shifting of at least one edge creating a concave corner from at least one of poly and active layers in response to the concave corner being at a space to the overlap of poly and active layers less than a predetermined value.
9. The method of claim 1, wherein modifying the target design further includes utilizing at least one of design rule checking (DRC) and layout versus schematic (LVS) software functions to verify that the design modifications have not violated predetermined design rules or circuit functionality.
10. The method of claim 9, wherein verification that the design modifications have not violated predetermined design rules or circuit functionality further includes removing the design modifications in response to a detection of violations.
11. The method of claim 1, wherein the first movement includes moving predetermined feature edges by upsizing features to be larger in a wafer circuit pattern than the corresponding features as drawn in a design database.
12. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a target design; and
modifying the target design to create an altered target design database in response to the results of the space checks, wherein modifying the target design includes a first movement of a group of at least one edge on a feature within the target design to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed, and wherein modifying the target design further includes a second movement of a group of at least one edge on a feature to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed in response to the first movement of edges, wherein the first movement includes moving predetermined feature edges by moving an edge of a line-end outward and moving an edge of an interacting feature inward.
13. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a design; and
modifying at least one of a contact, via or implant target design layers of the target design in response to results of the at least one of the space checks to create an altered target design database, wherein modifying the design includes moving at least one or more predetermined edges of a feature on the at least one of the contact, via or implant target design layers in order to decrease a risk of at least one of feature widths, feature spaces, feature electrical conductivity and feature enclosures being manufactured smaller than designed, wherein moving predetermined feature edges includes determining if the interconnect area enclosing a predetermined number of vias is greater than a predetermined value and upsizing the via to reduce the risk of the via conductivity being manufactured less than a predetermined value.
14. The method of claim 13, wherein modifying the target design includes utilizing at least one of design rule checking (DRC), rule-based optical proximity correction (RB-OPC) and model-based optical proximity correction (MB-OPC) software functions in order to move edges.
15. The method of claim 13, wherein shifting at least one edge of a via causes at least one of the position of the center of the via to be shifted and the shape of the via in the design database to become non-square.
16. The method of claim 13, wherein shifting at least one edge of a via includes at least partially merging at least two electrically connected vias.
17. The method of claim 13, wherein moving predetermined feature edges further includes the expanding of at least one edge outwards greater than one time and performing a subtraction operation between the expanded edges to create a sub-resolution assist feature.
18. The method of claim 17, wherein the sub-resolution assist feature is created to reduce the amount of obliquely reflected light incident from a reflective substrate upon a photoresist feature during a photolithography process.
19. The method of claim 13, wherein moving predetermined feature edges further includes optimization of the distance at which feature edges are moved based upon mask error factor (MEF) information.
20. The method of claim 13, wherein modifying the design further includes the use of at least one of design rule checking (DRC) and layout versus schematic (LVS) software functions to verify that the design modifications have not violated predetermined design rules or circuit functionality.
21. The method of claim 13, wherein modifying the design further includes shifting an edge of an implant feature to reduce the risk of dopant interdiffusion between opposite polarity implant regions.
22. The method of claim 13, wherein moving predetermined feature edges includes upsizing features to be larger in a wafer circuit pattern than the corresponding features as drawn in the design database.