Author: claimsbot

1. A data searching system comprising:
a routing table for storing a plurality of next-hop addresses:
a cache memory storing an IP flow table for storing at least one next-hop address which has been selected from the routing table: and
an address pointer table for storing location information indicating an entry address of each next-hop address stored in the IP flow table and relationship information among entry addresses of next-hop address stored in the IP flow table, wherein the address pointer table comprises a plurality of memory blocks each having a fixed length on a recording medium, located at consecutive addresses,
each memory block comprising:
a first area for storing an entry address indicating a location of a corresponding piece of data stored in the IP flow table; and
a second area for storing one of a next block address and a bottom-indicating flag, the next block address indicating an address of a memory block storing data following the corresponding piece of data, and the bottom-indicating flag indicating that a current memory block is a bottom of a list.
2. The data searching system according to claim 1, further comprising:
a controller controlling such that the IP flow table is searched for a desired next-hop address before the routing table and, if a hit is found in the IP flow table, then a found next-hop address is used as a search result, and if no hit is found in the cache memory storing the IP flow table, then the routing table is searched for the desired next-hop address and a found next-hop address is used as a search result and is registered into the IP flow table, wherein a next-hop address with low retrieved frequency is deleted from the IP flow table according to a predetermined condition and all linked memory blocks related to the deleted piece of data are released into available memory blocks.
3. A packet processing system comprising:
a microprocessor;
a routing table;
a cache memory storing an IP flow table which is used to increase search speed for packet forwarding; and
an address pointer table for storing location information indicating an entry address of each piece of data stored in the IP flow table and relationship information among entry addresses of pieces of data stored in the IP flow table, wherein the address pointer table comprises a plurality of memory blocks each having a fixed length on a recording medium, located at consecutive addresses.
each memory block comprising:
a first area for storing an entry address indicating a location of a corresponding piece of data stored in the IP flow table; and
a second area for storing one of a next block address and a bottom-indicating flag, the next block address indicating an address of a memory block storing data following the corresponding piece of data, and the bottom-indicating flag indicating that a current memory block is a bottom of a list.
4. A packet processing system comprising:
a microprocessor;
a routing table;
a searcher having a cache memory connected thereto, wherein the cache memory stores a search table to increase search speed for packet forwarding; and
an address pointer table for storing location information indicating an entry address of each piece of data stored in the search table and relationship information among entry addresses of pieces of data stored in the search table, wherein the address pointer table comprises a plurality of memory blocks each having a fixed length on a recording medium, located at consecutive addresses,
each of the memory blocks comprises:
a first area for storing an entry address indicating a location of a corresponding piece of data stored in the search table; and
a second area for storing one of a next block address and a bottom-indicating flag, the next block address indicating an address of a memory block storing data following the corresponding piece of data, and the bottom-indicating flag indicating that a current memory block is a bottom of a list.
5. The packet processing system according to claim 4, wherein the address pointer table is provided in a main memory of the microprocessor.
6. The packet processing system according to claim 4, wherein the address pointer table is provided in the cache memory.
7. A control method for controlling a packet processing system comprising:
a microprocessor;
a routing table;
a searcher having a cache memory connected thereto, wherein the cache memory stores a search table to increase in search speed for packet forwarding; and
an address pointer table for storing location information indicating an entry address of each piece of data stored in the search table and relationship information among entry addresses of pieces of data stored in the search table,
the control method comprising:
a) when the routing table has been updated, accessing the address pointer table based on contents of an entry to be changed to obtain location information of the entry to be changed and entries related to the entry to be changed in the cache memory; and
b) changing the entry and related entries so as to be consistent with the routing table,
wherein the address pointer table comprises a plurality of memory blocks each having a fixed length on a recording medium, located at consecutive addresses,
each memory block comprising:
a first area for storing an entry address indicating a location of a corresponding piece of data stored in the IP flow table; and
a second area for storing one of a next block address and a bottom-indicating flag, the next block address indicating an address of a memory block storing data following the corresponding piece of data, and the bottom-indicating flag indicating that a current memory block is a bottom of a list.
8. A system comprising:
a first memory for retrievably storing a plurality of next-hop address entries;
a cache memory for storing a copy of a next-hop address entry that has been retrieved from the first memory to retrievably store a plurality of retrieved next-hop address entries;
a second memory for storing a list of retrieved next-hop address entries which are linked from a leading one to a bottom one; and
a data controller for accessing a desired retrieved next-hop address entry by referring to the list stored in the second memory.
9. The system according to claim 8, wherein the data controller processes the desired retrieved next-hop address entry so as to be consistent with a corresponding next-hop address entry stored in the first memory when the corresponding next-hop address entry has been processed.
10. The system according to claim 8, wherein each of the next-hop address entries stored in the first memory has a first indicator and a second indicator, the first indicator indicating which one of a single entry and an aggregated entry the entry relates to, wherein the aggregated entry has a plurality of single entries belonging thereto, and the second indicator indicating a leading address of the list in the third memory.
11. The system according to claim 10, wherein, when an aggregated entry stored in the first memory is designated, the data controller accesses the second memory depending on the second indicator of the aggregated entry to trace the list of single entries related to the aggregated entry so as to access the single entries related to the aggregated entry.
12. The system according to claim 11, wherein, when contents of the first memory have been updated, the data controller processes the single entries related to the aggregated entry so as to be consistent with the contents of the first memory.
13. The system according to claim 8, wherein the list of retrieved next-hop address entries comprises a plurality of memory blocks each corresponding to the retrieved entries, the memory blocks comprising an address of a corresponding retrieved entry in the cache memory and a next pointer indicating one of an address of a next memory block following the memory block and an address of the memory block itself.
14. A packet switching system comprising:
a routing table for retrievably storing a plurality of routing entries;
a cache memory for storing a flow table having a copy of a routing entry indicating a packet flow that has been retrieved from the routing table to retrievably store a plurality of retrieved packet flows;
an address pointer table for storing a list of retrieved packet flows which are linked from a leading one to a bottom one;
a search processor for accessing a desired retrieved packet flow in the flow table by referring to the list stored in the address pointer table; and
a microprocessor performing a packet routing control.
15. The packet switching system according to claim 14, wherein, when a routing entry has been designated to be processed according to predetermined routing processing, the search processor processes a corresponding retrieved packet flow in the flow table so as to be consistent with the designated routing entry stored in the routing table.
16. The packet switching system according to claim 14, wherein each of the routing entries stored in the routing table has a first indicator and a second indicator, the first indicator indicating which one of a single packet flow and an aggregated packet flow the routing entry relates to when the aggregated packet flow has a plurality of single packet flows belonging thereto, and the second indicator indicating a leading address of the list in the address pointer table.
17. The packet switching system according to claim 16, wherein, when an aggregated routing entry stored in the routing table is designated, the search processor accesses the address pointer table depending on the second indicator of the aggregated routing entry to trace the list of single packet flows related to the aggregated routing entry so as to access the single packet flows related to the aggregated routing entry.
18. The packet switching system according to claim 17, wherein the search processor processes the single packet flows related to the aggregated routing entry so as to be consistent with the routing table when the routing table has been updated.
19. The packet switching system according to claim 14, wherein the list of retrieved packet flows comprises a plurality of memory blocks each corresponding to the retrieved packet flows, the memory blocks comprising an address of a corresponding retrieved packet flow in the flow table and a next pointer indicating one of an address of a next memory block following the memory block and an address of the memory block itself.
20. A packet switching method comprising:
a) retrievably storing a plurality of routing entries in a routing table;
b) storing a copy of a routing entry indicating a packet flow that has been retrieved from the routing table to retrievably store a plurality of retrieved packet flows in a cache memory;
c) storing a list of retrieved packet flows which are linked from a leading one to a bottom one in an address pointer table; and
d) accessing a desired retrieved packet flow in the cache memory by referring to the list stored in the address pointer table.
21. The packet switching method according to claim 20, wherein the step (d) comprises:
when a packet flow corresponding to a received packet fails to be found in the cache memory, searching the routing table for the packet flow;
registering the found packet flow as a routing result into the cache memory;
determining whether the found packet flow is a micro flow belonging to an aggregated flow;
when the found packet flow is the micro flow, searching the cache memory for a bottom retrieved packet flow of the list corresponding to the aggregated flow;
adding the found packet flow to the bottom retrieved packet flow stored in the cache memory; and
when the found packet flow is not the micro flow, storing an address of the found packet flow in the cache memory into a corresponding routing entry in the routing table.
22. The packet switching method according to claim 20, wherein the step (d) comprises:
when an aggregated routing entry has been designated to be deleted, deleting each of the retrieved packet flows included in a list related to the aggregated routing entry from the address pointer table until finding a bottom retrieved packet flow of the list;
releasing a chain of the retrieved packet flows formed in the address pointer table to make them available;
deleting a retrieved packet flow corresponding to the aggregated routing entry from the cache memory; and
deleting the aggregated routing entry from the routing table.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for providing wireless communication, the method comprising:
in a single coexistence terminal comprising at least a first communication device that handles a first communication protocol and a second communication device that handles a second communication protocol, communicating data via said first communication device utilizing a first polarized antenna; and
communicating data via said second communication device utilizing a second antenna that is orthogonally polarized with respect to said first polarized antenna.
2. The method according to claim 1, wherein said first communication device handles said first communication protocol selected from a group consisting of a Bluetooth (BT) protocol, a Wireless Local Area Network (WLAN) protocol, a cellular protocol, and a ZigBee protocol.
3. The method according to claim 2, wherein said second communication device handles said second communication protocol selected from a group consisting of said BT protocol, said WLAN protocol, said cellular protocol, and said ZigBee protocol excluding said selected said first communication protocol.
4. The method according to claim 1, wherein said communicated data is at least one of: Bluetooth (BT) protocol data, Wireless Local Area Network (WLAN) protocol data, cellular protocol data, and ZigBee protocol data.
5. The method according to claim 1, comprising transmitting said data via said first communication device utilizing said first polarized antenna.
6. The method according to claim 1, comprising transmitting said data via said second communication device utilizing said second antenna.
7. The method according to claim 1, comprising receiving said data via said first communication device utilizing said first polarized antenna.
8. The method according to claim 1, comprising receiving said data via said second communication device utilizing said second antenna.
9. A machine-readable storage having stored thereon, a computer program having at least one code section for providing wireless communication, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
in a single coexistence terminal comprising at least a first communication device that handles a first communication protocol and a second communication device that handles a second communication protocol, communicating data via said first communication device utilizing a first polarized antenna; and
communicating data via said second communication device utilizing a second antenna that is orthogonally polarized with respect to said first polarized antenna.
10. The machine-readable storage according to claim 9, wherein said first communication device handles said first communication protocol selected from a group consisting of a Bluetooth (BT) protocol, a Wireless Local Area Network (WLAN) protocol, a cellular protocol, and a ZigBee protocol.
11. The machine-readable storage according to claim 10, wherein said second communication device handles said second communication protocol selected from a group consisting of said BT protocol, said WLAN protocol, said cellular protocol, and said ZigBee protocol excluding said selected said first communication protocol.
12. The machine-readable storage according to claim 9, wherein said communicated data is at least one of: Bluetooth (BT) protocol data, Wireless Local Area Network (WLAN) protocol data, cellular protocol data, and ZigBee protocol data.
13. The machine-readable storage according to claim 9, wherein said at least one code section comprises code for transmitting said data via said first communication device utilizing said first polarized antenna.
14. The machine-readable storage according to claim 9, wherein said at least one code section comprises code for transmitting said data via said second communication device utilizing said second antenna.
15. The machine-readable storage according to claim 9, wherein said at least one code section comprises code for receiving said data via said first communication device utilizing said first polarized antenna.
16. The machine-readable storage according to claim 9, wherein said at least one code section comprises code for receiving said data via said second communication device utilizing said second antenna.
17. A system for achieving diversity gain in a communication network, the system comprising:
in a single coexistence terminal comprising at least a first communication device that handles a first communication protocol and a second communication device that handles a second communication protocol, at least one circuit that enables communication of data via said first communication device utilizing a first polarized antenna; and
said at least one circuit enables communication of data via said second communication device utilizing a second antenna that is orthogonally polarized with respect to said first polarized antenna.
18. The system according to claim 17, wherein said first communication device handles said first communication protocol selected from a group consisting of a Bluetooth (BT) protocol, a Wireless Local Area Network (WLAN) protocol, a cellular protocol, and a ZigBee protocol.
19. The system according to claim 18, wherein said second communication device handles said second communication protocol selected from a group consisting of said BT protocol, said WLAN protocol, said cellular protocol, and said ZigBee protocol excluding said selected said first communication protocol.
20. The system according to claim 17, wherein said communicated data is at least one of: Bluetooth (BT) protocol data, Wireless Local Area Network (WLAN) protocol data, cellular protocol data, and ZigBee protocol data.
21. The system according to claim 17, wherein said at least one circuit enables transmission of said data via said first communication device utilizing said first polarized antenna.
22. The system according to claim 17, wherein said at least one circuit enables transmission of said data via said second communication device utilizing said second antenna.
23. The system according to claim 17, wherein said at least one circuit enables receiving of said data via said first communication device utilizing said first polarized antenna.
24. The system according to claim 17, wherein said at least one circuit enables receiving of said data via said second communication device utilizing said second antenna.

1. A reinforcing bar binding machine comprising:
a guide tube for guiding a wire from a wire reel mounted on a binding machine body;
a curl guide;
a wire cutting mechanism disposed between the guide tube and the curl guide;
a first guide pin that is disposed at an end portion of the guide tube or in a vicinity of the end portion of the guide tube, and guides an outer side surface which is an outer side of a wire curve;
a second guide pin that is disposed at the end portion of the guide tube or in a vicinity of the end portion of the guide tube, and guides an inner side surface which is an inner side of the wire curve; and
a third guide pin that is disposed inside of the curl guide and guides the outer side surface,
wherein the wire is brought into contact with the first guide pin, the second guide pin, and the third guide pin, when the wire is fed around a reinforcing bar.
2. The reinforcing bar binding machine according to claim 1, wherein the second guide pin is disposed between the guide tube and the wire cutting mechanism.
3. The reinforcing bar binding machine according to claim 1, wherein the first guide pin, the second guide pin, and the third guide pin are made of a material having higher hardness than the wire.
4. The reinforcing bar binding machine according to claim 1, wherein sectional shapes of the first guide pin, the second guide pin, and the third guide pin are noncircular.
5. The reinforcing bar binding machine according to claim 1, further comprising:
a wearing preventive plate which is provided on a side wall between the first guide pin and the second guide pin, and is made of a material having higher hardness than the wire.
6. The reinforcing bar binding machine according to claim 5, wherein the wearing preventive plate fits to a concave portion on the side wall, and a surface of the wearing preventive plate is pressed and fixed by a tip end of the first guide pin and a tip end of the second guide pin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of manufacturing a touch screen panel, comprising:
forming a plurality of electrode structures spaced apart from each other at predetermined regular intervals, each of the structures having a first electrode, a piezoelectric layer and a second electrode formed on a substrate;
segmenting the substrate at a predetermined intervals to include at least one of the electrode structures; and
attaching a first segmented electrode structure on a first peripheral area of a display panel; and
attaching a second segmented electrode structure on a second peripheral area of the display panel so as to receive a surface acoustic wave signal of predetermined frequency from the first segmented electrode structure,
wherein the attaching a first segmented electrode structure and the attaching a second segmented electrode structure are performed using an adhesive member.
2. The method as set forth in claim 1, wherein forming the electrode structures comprises:
forming the first electrode on the front surface of the substrate using a first metallic layer;
forming the piezoelectric layer on a front surface of the first electrode; and
forming the second electrode on a front surface of the piezoelectric layer using a second metallic layer.
3. The method as set forth in claim 2, wherein the substrate is a flexible substrate or a rigid substrate.
4. The method as set forth in claim 2, wherein the first and the second metallic layers comprise low-resistance conductive material.
5. The method as set forth in claim 2, wherein the first and the second metallic layers are selected from the group consisting of aluminum (Al), copper (Cu), silver (Ag), gold (Au), indium tin oxide (ITO) and indium zinc oxide (IZO).
6. The method as set forth in claim 2, wherein the first and the second electrodes are formed by forming the first metallic layer or the second metallic layer using a sputtering method, performing radiation using an ultraviolet laser to pattern the first metallic layer and the second metallic layer in a rectangular shape or a chevron shape.
7. The method as set forth in claim 2, wherein the piezoelectric layer comprise ceramic material having a high melting point.
8. The method as set forth in claim 2, wherein the piezoelectric layer is selected from the group consisting of AlN, ZnO, lead zirconate titanate (PZT) and LiNbO3.
9. The method as set forth in claim 2, wherein the piezoelectric layer is automatically patterned through deposition using a metal mask, or is patterned using a photolithography and etching process.
10. The method as set forth in claim 2, further comprising forming a protective layer on a front surface of the second electrode.
11. The method as set forth in claim 1, wherein forming the electrode structures comprises:
forming the piezoelectric layer on the front surface of the substrate; and
forming a metallic layer on a front surface of the piezoelectric layer so that the opposite sides of the metallic layer are spaced apart from each other by a predetermined interval.
12. The method as set forth in claim 11, further comprising forming a protective layer on front surfaces of the first and second electrodes.
13. The method as set forth in claim 1, wherein the first and the second segmented electrode structures are attached to a border of the front surface of the image display unit.
14. A display device comprising:
a display panel;
an ultrasonic wave excitation transducer formed on a first substrate and attached to a peripheral region of the display panel using an adhesive member; and
an ultrasonic wave detection transducer formed on a second substrate and attached to the peripheral region of the display panel using the adhesive member so as to receive a surface acoustic wave signal of a predetermined frequency from the ultrasonic wave excitation transducer.
15. The display as set forth in claim 14, wherein the display is a liquid crystal display, a plasma display panel, or an organic light emitting diode display.
16. The display as set forth in claim 15, wherein the ultrasonic wave excitation transducer and the ultrasonic wave detection transducers are attached to an outer surface of a substrate which contains display electrodes on the inside surface of the plasma display panel.
17. The display as set forth in claim 15, wherein the ultrasonic wave excitation transducer and the ultrasonic wave detection transducers are attached to an outer surface of a substrate for manufacture of drive circuits of the organic light emitting diode display.
18. The display as set forth in claim 15, wherein the liquid crystal display comprises a thin film transistor substrate and a color filter substrate, and the ultrasonic wave excitation transducer and the ultrasonic wave detection transducers are attached to at least one of the thin-film transistor substrate or the color filter substrate.
19. The display as set forth in claim 14, wherein the display panel comprises a thin film transistor substrate and a color filter substrate, and the ultrasonic wave excitation transducer and the ultrasonic wave detection transducers are attached to at least one of the thin-film transistor substrate or the color filter substrate.
20. A display device comprising:
a display panel;
an ultrasonic wave excitation transducer formed on a first substrate and attached to a peripheral region of the display panel; and
an ultrasonic wave detection transducer formed on a second substrate and attached to the peripheral region of the display panel so as to receive a surface acoustic wave signal of a predetermined frequency from the ultrasonic wave excitation transducer,
wherein the display panel comprises a thin film transistor substrate and a color filter substrate, and
wherein a first polarizer is formed between the thin film transistor substrate and the color filter substrate.
21. The display as set forth in claim 20, wherein the first polarizer is formed on an opposite side of the color filter substrate where the ultrasonic wave excitation transducer and the ultrasonic wave detection transducer is attached.
22. The display as set forth in claim 21, further comprising a second polarizer formed on the thin film transistor substrate.
23. The display as set forth in claim 22, wherein the second polarizer is formed on a first side of the thin film transistor substrate on which a predetermined structure is formed.
24. The display as set forth in claim 22, wherein the second polarizer is formed between the thin film transistor substrate and a backlight unit below the thin-film transistor substrate.