Author: claimsbot

1. A system for driving a plurality of cold-cathode fluorescent lamps, the system comprising:
a subsystem configured to receive at least a DC voltage and generate a first AC voltage in response to at least the DC voltage;
a power converter configured to receive the first AC voltage and convert the first AC voltage to at least a second AC voltage; and
a plurality of current balancing devices;
wherein the power converter and the plurality of current balancing devices are configured to be directly or indirectly coupled to a plurality of cold-cathode fluorescent lamps including N fluorescent lamps;
wherein:
the plurality of cold-cathode fluorescent lamps includes a 1st fluorescent lamp, a 2nd fluorescent lamp, . . . , a (j\u22121)th fluorescent lamp, a jth fluorescent lamp, a (j+1)th fluorescent lamp, . . . , an (n\u22121)th fluorescent lamp, and an nth fluorescent lamp;
the 1st fluorescent lamp, the 2nd fluorescent lamp, . . . , the (j\u22121)th fluorescent lamp, the jth fluorescent lamp, the (j+1)th fluorescent lamp, . . . , the (n\u22121)th fluorescent lamp, and the nth fluorescent lamp are associated with a 1st lamp current, a 2nd lamp current, . . . , a (j\u22121)th lamp current, a jth lamp current, a (j+1)th lamp current, . . . , an (n\u22121)th lamp current, and an nth lamp current, respectively;
n\u22673; and
1<j<n;

wherein:
each of the plurality of current balancing devices is configured to receive two currents and balance the two currents;
the plurality of current balancing devices are further configured to balance the 1st lamp current and the 2nd lamp current, . . . , the (j\u22121)th lamp current and the jth lamp current, the jth lamp current and the (j+1)th lamp current, . . . , the (n\u22121)th lamp current and the nth lamp current, and the nth lamp current and the 1st lamp current, different pairs of currents being balanced by different current balancing devices;

wherein:
each of the plurality of current balancing devices includes a first winding and a second winding;
the first winding is in series with one of the plurality of cold-cathode fluorescent lamps; and
the second winding is in series with another one of the plurality of cold-cathode fluorescent lamps.
2. The system of claim 1 wherein the 1st lamp current, the 2nd lamp current, . . . , the (j\u22121)th lamp current, the jth lamp current, the (j+1)th lamp current, . . . , the (n\u22121)th lamp current, and the nth lamp current are input currents flowing into the 1st fluorescent lamp, the 2nd fluorescent lamp, . . . , the (j\u22121)th fluorescent lamp, the jth fluorescent lamp, the (j+1)th fluorescent lamp, . . . , the (n\u22121)th fluorescent lamp, and the nth fluorescent lamp, respectively.
3. The system of claim 1 wherein the 1st lamp current, the 2nd lamp current, . . . , the (j\u22121)th lamp current, the jth lamp current, the (j+1)th lamp current, . . . , the (n\u22121)th lamp current, and the nth lamp current are output currents flowing out of the 1\u2032 fluorescent lamp, the 2nd fluorescent lamp, the (j\u22121)th fluorescent lamp, the jth fluorescent lamp, the (j+1)th fluorescent lamp, . . . , the (n\u22121)th fluorescent lamp, and the nth fluorescent lamp, respectively.
4. The system of claim 1 wherein the power converter is further configured to drive the plurality of cold-cathode fluorescent lamps with at least the second AC voltage.
5. The system of claim 1 wherein the power converter is further configured to convert the first AC voltage to at least the second AC voltage and a third AC voltage.
6. The system of claim 5 wherein the power converter is further configured to drive the plurality of cold-cathode fluorescent lamps with at least the second AC voltage and the third AC voltage.
7. The system of claim 5 wherein the power converter includes at least a first transformer and a second transformer, the first transformer being configured to output the second AC voltage, the second transformer being configured to output the third AC voltage.
8. The system of claim 1 wherein the each of the plurality of current balancing devices is a current balance choke.
9. The system of claim 1, and further comprising a plurality of capacitors coupled to the power converter.
10. The system of claim 9 wherein the power converter is capable of being indirectly coupled to the plurality of cold-cathode fluorescent lamps through at least the plurality of capacitors.
11. The system of claim 1, and further comprising a current sensing feedback component coupled to the subsystem and configured to be coupled to at least one of the plurality of cold-cathode fluorescent lamps.
12. The system of claim 1 wherein the plurality of cold-cathode fluorescent lamps consists of an even number of cold-cathode fluorescent lamps.
13. The system of claim 1 wherein the plurality of cold-cathode fluorescent lamps consists of an odd number of cold-cathode fluorescent lamps.
14. A method for driving a plurality of cold-cathode fluorescent lamps, the method comprising:
receiving at least a DC voltage;
generating a first AC voltage in response to at least the DC voltage;
receiving the first AC voltage;
converting the first AC voltage to at least a second AC voltage;
driving a plurality of cold-cathode fluorescent lamps with at least the second AC voltage, the plurality of cold-cathode fluorescent lamps being associated with a plurality of lamp currents respectively;
balancing the plurality of lamp currents by a plurality of current balancing devices, each of the plurality of current balancing devices being configured to receive two currents and balance the two currents;
wherein:
the plurality of cold-cathode fluorescent lamps includes N fluorescent lamps;
the plurality of cold-cathode fluorescent lamps includes a 1st fluorescent lamp, a 2nd fluorescent lamp, . . . , a (j\u22121)th fluorescent lamp, a jth fluorescent lamp, a (j+1)th fluorescent lamp, . . . , an (n\u22121)th fluorescent lamp, and an nth fluorescent lamp;
the 1st fluorescent lamp, the 2nd fluorescent lamp, . . . , the (j\u22121)th fluorescent lamp, the jth fluorescent lamp, the (j+1)th fluorescent lamp, . . . , the (n\u22121)th fluorescent lamp, and the nth fluorescent lamp are associated with a 1st lamp current, a 2nd lamp current, . . . , a (j\u22121)th lamp current, a jth lamp current, a (j+1)th lamp current, . . . , an (n\u22121)th lamp current, and an nth lamp current, respectively;
n\u22673; and
1<j<n;

wherein the process for balancing the plurality of lamp currents by the plurality of current balancing devices includes balancing the 1st lamp current and the 2nd lamp current, . . . , the (j\u22121)th lamp current and the jth lamp current, the jth lamp current and the (j+1)th lamp current, . . . , the (n\u22121)th lamp current and the nth lamp current, and the nth lamp current and the 1st lamp current, different pairs of currents being balanced by different current balancing devices;
wherein:
each of the plurality of current balancing devices includes a first winding and a second winding; and
the process for balancing the plurality of lamp currents by the plurality of current balancing devices includes balancing one of the plurality of lamp currents by at least the first winding and another one of the plurality of lamp currents by at least the second winding.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory device, comprising:
a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage;
a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage from the first external power voltage; and
a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.
2. The device of claim 1, wherein the second external power voltage is higher in voltage level than the first external power voltage.
3. The device of claim 1, wherein the voltage boosting circuit power voltage generating circuit comprises:
a voltage boosting circuit reference voltage generating circuit for receiving the second external power voltage to generate the voltage boosting circuit reference voltage having a prescribed level; and
a voltage boosting circuit internal voltage driving circuit for generating the voltage boosting power voltage from the second external power voltage in response to the voltage boosting circuit reference voltage.
4. The device of claim 1, further comprising, a voltage boosting circuit for generating a boosted voltage using the voltage boosting circuit reference voltage and the voltage boosting circuit power voltage.
5. The device of claim 1, wherein the cell array internal voltage generating circuit comprises:
a cell array reference voltage generating circuit for receiving the first external power voltage to generate the cell array reference voltage having a prescribed level; and
a cell array internal voltage driving circuit for generating the cell array internal voltage from the first external power voltage according to the cell array reference voltage.
6. The device of claim 5, further comprising, a voltage boosting circuit for generating a boosted voltage using the cell array reference voltage and the voltage boosting circuit power voltage.
7. The device of claim 1, wherein the peripheral circuit internal voltage generating circuit comprises:
a peripheral circuit reference voltage generating circuit for receiving the first external power voltage to generate the peripheral circuit reference voltage having a prescribed level; and
a peripheral circuit internal voltage driving circuit for generating the peripheral circuit internal voltage from the first external power voltage according to the peripheral circuit reference voltage.
8. The device of claim 5, further comprising, a voltage boosting circuit for generating a boosted voltage using the peripheral circuit reference voltage and the voltage boosting circuit power voltage.
9. A semiconductor memory device, comprising:
a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage;
a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage from the first external power voltage; and
a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage from a second external power voltage and outputting the second external power voltage as a voltage boosting circuit power voltage.
10. The device of claim 9, wherein the second external power voltage is higher in voltage level than the first external power voltage.
11. The device of claim 9, further comprising, a voltage boosting circuit for generating a boosted voltage using the voltage boosting circuit reference voltage and the voltage boosting circuit power voltage.
12. The device of claim 9, wherein the cell array internal voltage generating circuit comprises:
a cell array reference voltage generating circuit for receiving the first external power voltage to generate the cell array reference voltage having a prescribed level; and
a cell array internal voltage driving circuit for generating the cell array internal voltage from the first external power voltage according to the cell array reference voltage.
13. The device of claim 12, further comprising, a voltage boosting circuit for generating a boosted voltage using the cell array reference voltage and the voltage boosting circuit power voltage.
14. The device of claim 9, wherein the peripheral circuit internal voltage generating circuit comprises:
a peripheral circuit reference voltage generating circuit for receiving the first external power voltage to generate the peripheral circuit reference voltage having a prescribed level; and
a peripheral circuit internal voltage driving circuit for generating the peripheral circuit internal voltage from the first external power voltage according to the peripheral circuit reference voltage.
15. The device of claim 14, further comprising, a voltage boosting circuit for generating a boosted voltage using the peripheral circuit reference voltage and the voltage boosting circuit power voltage.
16. A semiconductor memory device, comprising:
a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage;
a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage from the first external power voltage; and
a voltage boosting circuit for generating a boosted voltage using one of the cell array reference voltage and the peripheral circuit reference voltage, and a second external power voltage.
17. The device of claim 16, wherein the second external power voltage is higher in voltage level than the first external power voltage.

What is claimed is:

1. A processing device connected to a network and equipped with a browsing unit that displays supplied web pages on a display unit of the processing device, the processing device comprising:
a detection unit to communicate with the browsing unit and to detect whether a specific process is required for data input into a web page displayed by the browsing unit;
a processing unit to communicate with the detection unit and to execute specific processes on the data input into the web page responsive to a detection result by the detection unit; and
a control unit to communicate with the processing unit and to use results of the specific processes to process requests from the web page.
2. The processing device according to claim 1, wherein a search server connected to the network supplies the web pages and the processing unit translates the data input into the web page and the control unit sends a processing request to the search server using the translated data.
3. The processing device according to claim 2, further comprising
an administration unit to manage search servers;
a selection unit to select a search server from the search servers; and
a display control unit to cause the browsing unit to display a web page of the selected search server.
4. The processing device according to claim 3, further comprising a setting unit to add or delete a search server managed by the administration unit.
5. A computer-readable recording medium storing at least one computer program executed by a computer connected to a network, the computer having a browsing module displaying on a display unit of the computer supplied web pages, and said at least one computer program, comprising:
a detection module to detect whether a specific process is required for data input into a web page displayed by the browsing module;
a processing module to execute specific processes on the data responsive to a detection result by the detection module; and
a control module to use results of the specific processes when processing requests using the web page.
6. The computer-readable recording medium according to claim 5, wherein a search server connected to the network supplies the web pages and the processing module translates the data input into the web page and the control module sends a processing request to the search server using the translated data.
7. The computer-readable recording medium according to claim 6, further comprising
an administration module to manage search servers;
a selection module to select a search server from the search servers; and
a display control module to cause the browsing module to display a web page of the selected search server.
8. The computer-readable recording medium according to claim 7, further comprising a setting module to add or delete a search server managed by the administration module.
9. A processing device connected to a network and equipped with browsing means for displaying supplied web pages on display means of the processing device, the processing device comprising:
detection means for detecting whether a specific process is required for data input into a web page displayed by the browsing unit;
processing means for executing specific processes on the data input into the web page responsive to a detection result by the detection means; and
control means for using results of the specific processes to process requests from the web page.
10. The processing device according to claim 9, wherein a search server connected to the network supplies the web pages and the processing means translates the data input into the web page and the control means sends a processing request to the search server using the translated data.
11. A device connected to a network and displaying web pages supplied from a search server connected to the network, the device comprising:
a processor, to determine whether to translate a search query input into a web page, to translate the search query responsive to the determination, and to send the translated search query to the search server.
12. The device according to claim 11, wherein the processor further administers a list of search servers, selects a search server from the list of search servers, and displays a web page of the selected search server.
13. The device according to claim 12, wherein the processor further administers search query settings of each search server.
14. A client-server system, comprising
a search server connected to a network and to supply web pages;
a client connected to the network and comprising a processor, to display web pages supplied from the search server, to determine whether to translate a search query input into a web page, to translate the search query responsive to the determination, and to send the translated search query to the search server.
15. The device according to claim 14, wherein the processor further administers a list of search servers, selects a search server from list of search servers, and displays a web page of the selected search server.
16. The device according to claim 15, wherein the processor further administers search query settings of each search server.
17. A method of searching on a network web page information in one language via a search query in another language, comprising:
determining in a device connected to the network whether to translate a search query input into a web page, the search query being in one language to be sent to a search server connected to the network and the search server containing web page information in another language;
translating in the device the search query responsive to the determination; and
sending from the device the translated search query to the search server.
18. A device connected to a network and displaying web pages supplied from a server connected to the network, the device comprising:
a processor, to determine whether to perform a process on data input into a web page by a user, to perform the process responsive to the determination, and to send to the server processing requests of the web page using results of the process.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for storing image data configured to store a frame of said image data as a plurality of tiles, wherein at least one of said plurality of tiles comprises data from both a first and a second field of said frame.
2. The apparatus according to claim 1, wherein each of said plurality of tiles is divided into a plurality of sub-tiles, each of said sub-tiles comprising a plurality of lines of a respective tile.
3. The apparatus according to claim 2, wherein said plurality of lines comprises data from both said first and second fields.
4. The apparatus according to claim 1, wherein said apparatus comprises at least one of a video encoder, a video decoder, a video compressor, a video decompressor, a video CODEC.
5. A method for storing interlaced image data comprising the steps of:
dividing a frame of said image data comprising two fields into a plurality of tiles, wherein at least one of said plurality of tiles contains data from both fields; and
storing said plurality of tiles.
6. The method according to claim 5, further comprising the steps of:
dividing at least one of said plurality of tiles into a plurality of sub-tiles, wherein each sub-tile comprises a plurality of lines of a respective tile.
7. The method according to claim 6, wherein at least one of said plurality of sub-tiles comprises data from only a first one of said two fields and at least one other of said plurality of sub-tiles comprises data from only a second one of said two fields.
8. The method according to claim 6, wherein at least one of said plurality of sub-tiles comprises data from both of said two fields.
9. The method according to claim 6, wherein the storage of image data in said plurality of tiles is alternated between line pairs from opposite fields of said image in two separate storage devices.
10. The method according to claim 9, wherein two lines of a field are stored together.
11. The method according to claim 10, wherein the storage of image data in said plurality of tiles is alternated between even and odd lines of said frame, two at a time, in two separate storage devices.
12. The method according to claim 11, wherein a sub-tile of one of said plurality of tiles comprises data from two lines in said tile of one of said fields.
13. A method for storing image data comprising the steps of:
dividing a frame of said image data into a plurality of tiles; and
storing each of said plurality of tiles in a non-raster format.
14. The method according to claim 13, wherein at least one of said plurality of tiles comprises data from a first and a second field of said frame.
15. The method according to claim 13, further comprising the step of:
dividing at least one of said plurality of tiles into a plurality of sub-tiles, wherein each of said plurality of sub-tiles comprises one or more lines of a respective tile.
16. The method according to claim 15, wherein each sub-tile comprises 2 lines of a respective tile.
17. The method according to claim 15, wherein each sub-tile comprises 4 lines of a respective tile.
18. The method according to claim 15, wherein at least one sub-tile comprises data from a first and a second field of said frame.
19. The method according to claim 15, wherein:
at least one of said sub-tiles comprises data from only a first field of said frame; and
at least one other of said sub-tiles comprises data from only a second field of said frame.