Author: claimsbot

1. An integrated cryptographic apparatus providing confidentiality and integrity comprising:
an integrated cryptographic module including a confidentiality and an integrity performances;
a hash function unit for detecting whether a message is modified by using the integrated cryptographic module; and
a block cipher unit for constructing a data encryption algorithm by using the integrated cryptographic module.
2. The apparatus of claim 1, wherein the integrated cryptographic module generates outputs with respect to input bit string by using operations including S-box, circular movement, and XOR.
3. The apparatus of claim 1, wherein the hash function unit includes:
a message pre-processing unit converting an input bit string of an arbitrary length into a 32-bit word array;
a message compressing unit compressing the converted 32-bit word array; and
a hash value output unit outputting a hash value of a certain hash length by using a value output from the message compressing unit.
4. The apparatus of claim 3, wherein the message pre-processing unit adds one 1 and at least one 0 to a last bit so that the input bit string becomes a 32-bit multiple.
5. The apparatus of claim 3, wherein the message compressing unit sequentially compresses a message converted into a 32-bit word array by using a state updating function.
6. The apparatus of claim 5, wherein the state updating function updates an input by repeatedly applying the integrated cryptographic module to the input.
7. The apparatus of claim 3, wherein the hash value output unit performs a state updating function which corresponds to a length of the hash function.
8. The apparatus of claim 1, wherein the block cipher unit includes a function for outputting a 128-bit ciphertext by repeatedly applying the integrated cryptographic module to a 128-bit plaintext and a 128-bit key.
9. An integrated cryptographic method providing confidentiality and integrity comprising:
generating a hash function for detecting whether a message is modified by using an integrated cryptographic module including a confidentiality and an integrity performances; and
generating a block cipher for constructing a data cryptographic algorithm by using the integrated cryptographic module.
10. The method of claim 9, wherein the integrated cryptographic module generates outputs with respect to input bit string by using operations including S-box, circular movement, and XOR.
11. The method of claim 9, wherein said generating the hash function includes:
a message pre-processing for converting an input bit string of an arbitrary length into a 32-bit word array;
a message compressing for compressing the converted 32-bit word array; and
a hash value outputting for outputting a hash value of a certain hash length by using a value output from the message compressing unit.
12. The method of claim 11, wherein said message pre-processing adds one 1 and at least one 0 to a last bit so that the input bit string becomes a 32-bit multiple.
13. The method of claim 11, wherein said message compressing sequentially compresses a message converted into a 32-bit word array by using a state updating function.
14. The method of claim 13, wherein the state updating function updates an input by repeatedly applying the integrated cryptographic module to the input.
15. The method of claim 11, wherein said hash value outputting performs a state updating function which corresponds to a length of the hash function.
16. The method of claim 9, said generating the block cipher is a function for outputting a 128-bit ciphertext by repeatedly applying the integrated cryptographic module to a 128-bit plaintext and a 128-bit key.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of delivering an otic drug to the ear comprising the steps of
(a) preparing an otic composition comprising the otic drug and a carrier, wherein the carrier comprises a low molecular weight compound having a molecular weight of 150-4000, the carrier reversibly changes from solid to liquid at a temperature of 32-37\xb0 C., and the low molecular weight compound has the formula:
wherein R1 is \u2014H, \u2014OH, \u2014COOH, CnH2n+1-2m, COOCnH2n+1-2m, \u2014COO(CH2CH2O)nCH2CH2OH, \u2014CH2R3, or
R2, R3 and R4 are independently \u2014H, \u2014OH, \u2014COOH, \u2014CnH2n+1-2m,
\u2014OOCCnH2n+1-2m, \u2014COOCnH2n+1-2m, \u2014COO(CH2CH2O)nCH2CH2OH, \u2014CnH2n+1-2mCOO(CH2CH2O)nCH2CH2OH,
\u2014OOCCnH2n+1-2mCOOCn\u2032H2n\u2032+1-2m\u2032, \u2014COO\u2212Na+, \u2014COO\u2212K+, \u2014SO3H,
\u2014SO3\u2212Na+, \u2014SO3\u2212K+, \u2014NH2, \u2014Cl,
n, n\u2032 and n\u2033 are independently 0-50; and
m, m\u2032 and m\u2033 are independently 0-10,
and
(b) inserting the composition prepared in step (a) in the ear canal.
2. The method of claim 1, wherein the composition prepared in step (a) is dropped, injected, deposited, or sprayed into the external ear.
3. The method of claim 2 wherein the composition prepared in step (a) is warmed to a temperature above 32\xb0 C. and administered topically or locally as an ear drop or through a cannula.
4. The method of claim 1 wherein the composition prepared in step (a) does not contain any polymeric ingredient and the carrier consists essentially of one or more low molecular weight compounds of formula (I).
5. The method of claim 1 wherein the low molecular weight compound of formula (I) has a molecular weight \xb12000.
6. The method of claim 1 wherein
R1 is, \u2014CnH2n+1-2m, \u2014COOCnH2n+1-2m, \u2014COO(CH2CH2O)nCH2CH2OH, \u2014CH2R3, or
R2, R3 and R4 are independently \u2014H, \u2014OH, \u2014COOH, \u2014CnH2n+1-2m, OOCCnH2n+1-2m, \u2014COOCnH2n+1-2m, \u2014COO(CH2CH2O)nCH2CH2OH,
\u2014CnH2n+1-2mCOO(CH2CH2O)nCH2CH2OH, or \u2014OOCCnH2n+1-2mCOOCn\u2032H2n\u2032+1-2m\u2032;
n, n\u2032 and n\u2033 are independently 0-40; and
m, m\u2032 and m\u2033 are independently 0-5.
7. The method of claim 6 wherein
R1 is
R2, R3 and R4 are independently \u2014H, \u2014OH, \u2014COOH, \u2014CnH2n+1-2m, or \u2014OOCCnH2n\u22121-2m;
n, n\u2032 and n\u2033 are independently 0-30; and
m, m\u2032 and m\u2033 are independently 0-3.
8. The method of claim 1 wherein the total concentration of the low molecular weight compound of formula (I) in the composition prepared in step (a) is at least 10% (ww).
9. The method of claim 1 wherein the otic drug is one or more compounds selected from the group consisting of anti-infective agents; non-steroidal anti-inflammatory agents; steroidal anti-inflammatory agents; and anti-pain agents.

1. A semiconductor integrated circuit device comprising:
a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode;
a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer;
a first input line connected to the gate electrode of the first field-effect transistor;
a second input line connected to the gate electrode of the second field-effect transistor,
wherein:
the second input line is different from the first input line,
the substrate potential diffusion layer or the well potential diffusion layer is formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor, and
no isolation insulating film is disposed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor,
wherein the gate electrode of the first field-effect transistor is electrically isolated from the gate electrode of the second field-effect transistor.
2. The semiconductor integrated circuit device according to claim 1, wherein the substrate potential diffusion layer or the well potential diffusion layer is disposed to surround the source diffusion layer.
3. The semiconductor integrated circuit device according to claim 1, wherein the substrate potential diffusion layer or the well potential diffusion layer are connected with the source diffusion layer by a silicided diffusion layer.
4. The semiconductor integrated circuit device according to claim 3, further comprising a contact provided over a boundary line between the source diffusion layer and the substrate potential diffusion layer or the well potential diffusion layer.
5. The semiconductor integrated circuit device according to claim 3, wherein a contact is provided to only one of the source diffusion layer and the substrate potential diffusion layer or the well potential diffusion layer.
6. The semiconductor integrated circuit device according to claim 1, wherein at least one of the first and the second field-effect transistor is part of a flip-flop circuit or a latch circuit.
7. The semiconductor integrated circuit device according to claim 1, wherein the first field-effect transistor and the second field-effect transistor are part of a SRAM cell circuit.
8. The semiconductor integrated circuit device according to claim 1, further comprising:
a field-effect transistor of a first conductivity type corresponding to either the first field-effect transistor or the second field-effect transistor; and
a field-effect transistor of a second conductivity type,
wherein the a field-effect transistor of the first conductivity type has a gate electrode formed as a ring shape, a drain diffusion layer of the first conductivity type formed inside the gate electrode, a source diffusion layer of the first conductivity type formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer of a second conductivity type different from the first conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed outside the source diffusion layer to be in contact with the source diffusion layer of the first conductivity type;
the field-effect transistor of the second conductivity type has a gate electrode formed as a ring shape, a drain diffusion layer of the second conductivity type formed inside the gate electrode, a source diffusion layer of the second conductivity type formed outside the gate electrode and a well potential diffusion layer or a substrate potential diffusion layer of the first conductivity type different from the second conductivity type, the well potential diffusion layer or the substrate potential diffusion layer being formed outside the source diffusion layer to be in contact with the source diffusion layer of the second conductivity type,
the field-effect transistor of the first conductivity type is connected by a silicided diffusion layer to make the source diffusion layer of the first conductivity type be the same potential as the substrate potential diffusion layer or the well potential diffusion layer of the second conductivity type,
the field-effect transistor of the second conductivity type is connected by a silicided diffusion layer to make the source diffusion layer of the second conductivity type be the same potential as the well potential diffusion layer or the substrate potential diffusion layer of the first conductivity type, and
the field-effect transistor of the first conductivity type and the field-effect transistor of the second conductivity type satisfy either to input the same signal to each of the gate electrodes or that each of the drain diffusion layers are the same potential.
9. The semiconductor integrated circuit device according to claim 8, wherein the field-effect transistor of the first conductivity type and the field-effect transistor of the second conductivity type are adjacent with an insulating film which isolates a device interposed therebetween, and
the substrate potential diffusion layer or the well potential diffusion layer of the second conductivity type and the well potential diffusion layer or the substrate potential diffusion layer of the first conductivity type respectively contact the insulating film which isolates the device.
10. The semiconductor integrated circuit device according to claim 8, wherein the field-effect transistor of the first conductivity type and the field-effect transistor of the second conductivity type operate as an inverter circuit.
11. The semiconductor integrated circuit device according to claim 10, wherein the inverter circuit operates as a part of an oscillator having a plurality of the inverter circuits connected in series.
12. The semiconductor integrated circuit device according to claim 8, wherein a plurality of the field-effect transistors of the first conductivity type and a plurality of the field-effect transistors of the second conductivity type are formed without intervening an insulating film which isolates a device in a first direction parallel to a boundary surface between the field-effect transistor of the first conductivity type and the field-effect transistor of the second conductivity type.
13. The semiconductor integrated circuit device according to claim 8, wherein the plurality of the field-effect transistors of the first conductivity type are adjacent without intervening the substrate potential diffusion layer or the well potential diffusion layer of the second conductivity type in the first direction parallel to a boundary surface between the field-effect transistor of the first conductivity type and the field-effect transistor of the second conductivity type, and
the plurality of the field-effect transistors of the second conductivity type are formed to be adjacent without intervening the well potential diffusion layer or the substrate potential diffusion layer of the first conductivity type in the first direction.
14. A semiconductor integrated circuit device comprising:
a first field-effect transistor having a first gate electrode formed as a ring shape, a first drain diffusion layer formed inside the first gate electrode and a first source diffusion layer formed outside the first gate electrode;
a second field-effect transistor using the first source diffusion layer inside a second gate electrode formed as a ring shape outside the first gate electrode as a second drain diffusion layer and having a second source diffusion layer formed outside the second gate electrode; and
a substrate potential diffusion layer or a well potential diffusion layer of a conductivity type different from the second source diffusion layer formed in the periphery of the second source diffusion layer to be in contact with the second source diffusion layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A test fixture for an interlock plate of a fueling nozzle comprising:
a main body, said body having an annular rib projecting outwardly therefrom, said annular rib provided with spaced apart slots, whereby said annular rib may depress an interlock plate an amount equal to the depth of the slots.
2. The invention defined in claim 1 wherein said main body is in the shape of a cylinder.
3. The invention defined in claim 1 wherein said main body is in the shape of a hollow right circular cylinder.
4. The invention defined in claim 2 wherein the annular rib projects outwardly from an end of said body.
5. The invention defined in claim 4 wherein the annular rib is a continuation of said body.
6. The invention defined in claim 2 wherein the annular rib is substantially the same outside diameter as said body.
7. The invention defined in claim 2 wherein the slots formed in the rib have a depth of from 0.080 to 0.085 inch.
8. A method of testing an aircraft fuel nozzle for excessive wear in the interlock mechanism comprising the steps of:
depressing the interlock mechanism of a nozzle a predetermined amount in excess of that actually present to detect whether wear has occurred in the nozzle interlock mechanism.