Author: claimsbot

1. A nonvolatile semiconductor memory comprising:
a memory cell;
a bit line connected to one end of the memory cell; and
a data circuit which is connected to the bit line and in which program data or read data concerning the memory cell is temporarily stored,
wherein the data circuit includes: first, second, and third data storage units; a first data transfer circuit connected between the first and third data storage units; and a second data transfer circuit connected between the second and third data storage units,
the first data storage unit is connected to the bit line, and the second data storage unit includes a function of forcibly changing a value of a first data stored in the first data storage unit based on a second data stored in the second data storage unit, and
the third data storage unit stores a third data different from the first data while the second data storage unit forcibly changes the value of the first data.
2. A nonvolatile semiconductor memory according to claim 1, wherein the first and second data storage units are constituted of capacitors.
3. A nonvolatile semiconductor memory according to claim 1, wherein the first data storage unit is constituted of a MOS capacitor.
4. A nonvolatile semiconductor memory according to claim 1, wherein the second data storage unit is constituted of a MOS transistor whose gate is connected to the second data transfer circuit, and a third data transfer circuit is connected between a drain of the MOS transistor and the first data storage unit.
5. A nonvolatile semiconductor memory according to claim 4, wherein the data circuit further includes: a fourth data storage unit connected to a data line via a column selection switch; and a fourth data transfer circuit connected between the first and fourth data storage units.
6. A nonvolatile semiconductor memory according to claim 5, wherein the fourth data storage unit is constituted of a latch circuit.
7. A nonvolatile semiconductor memory according to claim 6, wherein the latch circuit is constituted of a CMOS flip-flop circuit.
8. A nonvolatile semiconductor memory according to claim 5, wherein the third and fourth data transfer circuits are constituted of MOS transistors.
9. A nonvolatile semiconductor memory according to claim 5, further comprising: a control circuit which controls movement of the read data in the data circuit.
10. A nonvolatile semiconductor memory according to claim 9, wherein with respect to the memory cell which has four states, the control circuit includes: means for storing first read data read from the memory cell at a first read potential into the third data storage unit; means for transferring the first read data to the second data storage unit from the third data storage unit; means for storing second read data read from the memory cell at a second read potential into the first data storage unit; means for forcibly changing a value of the second read data stored in the first data storage unit based on the first read data stored in the second data storage unit; and means for transferring the second read data to the fourth data storage unit from the first data storage unit.
11. A nonvolatile semiconductor memory according to claim 5, further comprising: a control circuit which controls movement of the program data in the data.
12. A nonvolatile semiconductor memory according to claim 11, wherein the control circuit includes: means for storing the program data into the fourth data storage unit; means for transferring the program data to the third data storage unit from the fourth data storage unit; and means for transferring the program data to the second data storage unit from the third data storage unit.
13. A nonvolatile semiconductor memory according to claim 12, wherein with respect to the memory cell which has a function of storing two bit data and in which one bit data of the data is already stored, the control circuit includes: means for transferring the program data to the third data storage unit from the fourth data storage unit and subsequently resetting a state of the fourth data storage unit; and means for reading the one bit data stored in the memory cell into the fourth data storage unit.
14. A nonvolatile semiconductor memory according to claim 13, wherein the control circuit includes: means for storing the read data into the first data storage unit by verify read; means for forcibly changing the value of the read data stored in the first data storage unit in accordance with the value of the one bit data stored in the fourth data storage unit; and means for storing the read data stored in the first data storage unit as the program data into the third data storage unit.
15. A nonvolatile semiconductor memory according to claim 12, wherein the control circuit includes means for determining whether or not the threshold voltage of the memory cell is fluctuated based on the value of the program data stored in the third data storage unit at a writer operation time.
16. A nonvolatile semiconductor memory according to claim 15, wherein the value of the program data stored in the third data storage unit is changed in accordance with the data read from the memory cell by verify read.
17. A nonvolatile semiconductor memory according to claim 16, wherein the value of the program data stored in the second data storage unit does not always change.
18. A nonvolatile semiconductor memory according to claim 17, wherein the control circuit includes: means for resetting a state of the third data storage unit after completion of programming with respect to the memory cell; and means for transferring the program data stored in the second data storage unit to the third data storage unit.
19. A nonvolatile semiconductor memory according to claim 1, wherein the third data storage unit is constituted of a latch circuit.
20. A nonvolatile semiconductor memory according to claim 19, wherein the latch circuit is constituted of a CMOS flip-flop circuit.
21. A nonvolatile semiconductor memory according to claim 1, wherein the data circuit further includes: a clamp circuit connected between the bit line and first data storage unit; and a precharge circuit connected to the first data storage unit.
22. A nonvolatile semiconductor memory according to claim 1, further comprising: a detection circuit which judges presenceabsence of completion of a program with respect to the memory cell based on the data stored in the third data storage unit.
23. A nonvolatile semiconductor memory according to claim 1, wherein the first and second data transfer circuits are constituted of MOS transistors.
24. A nonvolatile semiconductor memory according to claim 1, wherein the memory cell stores two bits or more data.
25. A nonvolatile semiconductor memory according to claim 1, wherein the memory cell is a nonvolatile memory cell including a floating gate electrode and control gate electrode.
26. A nonvolatile semiconductor memory according to claim 1, wherein for the program data stored in the second and third data storage units, in order to determine whether or not the threshold voltage of the memory cell is fluctuated based on the value of the program data stored in the third data storage unit at a write operation time, the control circuit includes: means for storing the read data into the first data storage unit by verify read; means for forcibly changing the value of the read data stored in the first data storage unit in accordance with the value of the program data stored in the second data storage unit; and means for storing the read data stored in the first data storage unit as the program data into the third data storage unit.
27. A nonvolatile semiconductor memory comprising:
a nonvolatile semiconductor memory cell which can electrically be rewritten;
a bit line connected to the memory cell;
a read circuit which reads out data of the memory cell and which includes a first data storage unit connected to the bit line, a second data storage unit having a function of forcibly changing a value of a first data stored in the first data storage unit in accordance with a second data stored in the second data storage unit, a third data storage unit having a function of latching a third data, and a data transfer circuit to transfer the third data stored in the third data storage unit to the second data storage unit; and
a read control circuit which reads a read data as the first data from the memory cell into the first data storage unit via the bit line, forcibly changes a value of the read data stored in the first data storage unit in accordance with the second data and the third data storage unit stores the third data different from the read data while the second data storage unit forcibly changes the value of the read data.
28. A nonvolatile semiconductor memory according to claim 27, wherein the first and second data storage units accumulate electric charges into capacitors to store the data.
29. A nonvolatile semiconductor memory according to claim 28, wherein the data transfer circuit is constituted of a first MOS transistor, the second data storage unit is constituted of a second MOS transistor, a source of the second MOS transistor is connected to a first electrode of a capacitor of the first data storage unit via a third MOS transistor, and a gate of the second MOS transistor is connected to the source of the first MOS transistor.
30. A nonvolatile semiconductor memory according to claim 29, wherein the third data storage unit is constituted of two CMOS flip-flops, connected to a drain of the first MOS transistor, and further connected to the first electrode of the capacitor of the first data storage unit via a fourth MOS transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of transferring heat from a body portion of a mammal comprising the acts of:
determining a state of vasoconstriction or vasodilation in a portion of a body;
supplying heat to the portion of the body when vasoconstriction is determined; and
removing heat from the portion of the body when vasodilation is determined.
2. The method of approach 1, wherein the portion of the body is an arterial vascular anastamosis containing portion of the body.
3. The method of approach 1, further including the act of preselecting the portion of the body.
4. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation includes sensing a characteristic of the body associated with the state of vasoconstriction or vasodilation.
5. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation includes measuring blood flow.
6. The method of approach 5, wherein the act of measuring blood flow further includes measuring a volume of the portion of the body.
7. The method of approach 5, wherein the act of measuring blood flow further includes measuring blood flow by laser Doppler.
8. The method of approach 5, wherein a state of vasoconstriction is associated with a first range of blood flow levels and vasodilation is associated with a second range of blood flow levels.
9. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring heat transfer from the portion of the body.
10. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring the temperature of the body.
11. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring the core body temperature.
12. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring tympanic temperature.
13. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring skin temperature of a portion of the body.
14. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring bio-impedance of a portion of the body.
15. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes measuring light absorption of a portion of the body.
16. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes providing an EKG.
17. The method of approach 1, wherein the act of determining vasoconstriction or vasodilation further includes providing an ECG.
18. The method of approach 1, further including the act of controlling at least one of vasoconstriction or vasodilation.
19. The method of approach 18, wherein controlling at least one of vasoconstriction or vasodilation includes the act of inducing vasodilation in a portion of the body.
20. The method of approach 18, wherein controlling at least one of vasoconstriction or vasodilation includes the act of inducing vasoconstriction in a portion of the body.
21. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes applying a surface treatment to the portion of the body.
22. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes influencing the thermoregulatory system of the mammal.
23. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes influencing the Pre-Optic Anterior Hypothalamus (POAH) of the mammal.
24. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes providing at least one preselected visual stimulus.
25. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes drug delivery.
26. The method of approach 18, wherein the act of controlling at least one of vasoconstriction or vasodilation includes adjusting the temperature of the portion of the body.
27. The method of approach 1, wherein the act of supplying heat further includes supplying sufficient heat to effect vasodilation.
28. The method of approach 1, further including the act of applying negative pressure to the portion of the body.
29. A method of transferring heat from a body portion of a mammal comprising the acts of:
inducing a transition of a body portion from a state of vasodilation to vasoconstriction by removing heat from the body portion;
determining a transition temperature associated with the transition from vasodilation to vasoconstriction;
reestablishing vasodilation in the body portion; and
removing heat from the body portion with a temperature equal to or greater than the transition temperature.
30. The method claim 29, wherein if the body portion is initially in vasoconstriction, supplying heat until vasodilation occurs before inducing the transition from vasodilation to vasoconstriction.
31. The method of claim 29, wherein the temperature is within 2\xb0 C. of the transition from vasodilation to vasoconstriction.
32. The method of claim 29, wherein the temperature is within 1\xb0 C. of the transition from vasodilation to vasoconstriction.
33. The method of claim 29, wherein the temperature is lowered after reestablishing vasodilation without inducing vasoconstriction.
34. (canceled)
35. A method of transferring heat to or from a portion of a body of a mammal comprising the acts of:
determining a state of vasoconstriction or vasodilation in a portion of the body;
when vasodilation is determined, selecting transferring heat to or from the portion of the body; and
when vasoconstriction is determined, selecting at least one of supplying heat to the portion of the body and not removing heat from the portion of the body,
whereby optimal thermoregulatory status of the mammal is maintained.
36. (canceled)
37. A method for controlling the body temperature of a mammal comprising:
removing or supplying heat from a portion of the body,
while maintaining the portion of the body above a temperature causing vasoconstriction in the portion of the body by a means for control employing a measured characteristic associated with a state of vasoconstriction or vasodilation of the portion of the body.
38. The method of approach 37, wherein the temperature of the portion of the body is maintained above 18\xb0 C. to 22\xb0 C.
39. The method of approach 37, further including the act of maintaining the temperature of the portion of the body below approximately 25\xb0 C.
40. A method of controlling body temperature of a mammal comprising:
placing at least a portion of the body in thermal communication with a conductor;
measuring a characteristic associated with a state of vasoconstriction or vasodilation in the portion of the body; and
controlling heating or cooling of the conductor to maintain vasodilation in the portion of the body based upon a value that relates the characteristic to vasodilation.
41. The method of approach 40, wherein the value is determined by supplying heat until vasodilation occurs,
removing heat until vasoconstriction occurs,
reestablishing vasodilation, and
setting the value equal to or greater than a value corresponding to the transition from vasodilation to vasoconstriction.
42. The method of approach 41, wherein the value is associated with a temperature of the conductor greater than or equal to a temperature where a transition of vasodialtion to vasoconstriction occurs.
43. A system for controlling body temperature of a mammal comprisiong:
a conductor adapted to interface with a body portion of the mammal;
a controller adapted to vary a temperature o the conductor;
a sensor element for sensing a characteristic associated with vasoconstriction or vasodilation of the body portion,
wherein the controller adjusts the temperature of the conductor to maintain vasodilation in the portion of the body portion based upon a predetermined schedule that relates to the characteristic to vasodilation.
44. The system of claim 43, further including a heat exchange medium in thermal communication with at least a portion of the mammal and with at least a portion of the conductor.
45. (canceled)

1. A method comprising:
receiving, at a pulse width modulation (PWM) signal generator, an input PWM signal; and
generating, at the PWM signal generator and based on the input PWM signal, multiple output PWM signals that have duty ratios substantially equal to a duty ratio of the input PWM signal and that are synchronized to a synchronization signal and that have predetermined phase-shifts in relation to each other, and such that a PWM cycle of a leading output PWM signal of the multiple output PWM signals is prematurely terminated in response to a synchronization event represented by the synchronization signal so as to result in a prematurely-terminated PWM cycle for the leading output PWM signal and such that the prematurely-terminated PWM cycle is replicated for each non-leading PWM signal of the multiple output PWM signals while maintaining the predetermined phase-shifts between the multiple output PWM signals.
2. The method of claim 1, further comprising:
controlling a plurality of light emitting diode (LED) strings using the multiple output PWM signals.
3. The method of claim 1, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
4. The method of claim 1, wherein the PWM cycle comprises a first PWM cycle and generating the multiple output PWM signals comprises:
initiating generation of the first PWM cycle for a first set of intermediate PWM signals at a first signal generation unit of the PWM signal generator, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
prematurely terminating generation of the first PWM cycle for a leading intermediate PWM signal of the first set in response to the synchronization event;
replicating a completed portion of the first PWM cycle for the leading intermediate PWM signal for the first PWM cycle of each non-leading intermediate PWM signal of the first set;
generating a second PWM cycle for a second set of intermediate PWM signals at a second signal generation unit of the PWM signal generator in response to the synchronization event, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and
combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set to generate the multiple output PWM signals.
5. The method of claim 4, further comprising:
generating a third PWM cycle for a third set of intermediate PWM signals at a third signal generation unit of the PWM signal generator in response to a completion of the second PWM cycle; and
wherein combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set comprises combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set and a corresponding intermediate PWM signal of the third set to generate the multiple output PWM signals.
6. The method of claim 4, further comprising:
sampling, at the PWM signal generator, a first PWM cycle of the input PWM signal to determine a first value representative of a duty ratio of the first PWM cycle of the input PWM signal;
sampling, at the PWM signal generator, a second PWM cycle of the input PWM signal following the first PWM cycle of the input PWM signal to determine a second value representative of a duty ratio of the second PWM cycle of the input PWM signal;
wherein initiating generation of the first PWM cycle for the first set of intermediate PWM signals comprises timing generation of active segments of the first PWM cycle for each intermediate PWM signal of the first set based on the first value; and
wherein generating the second PWM cycle for the second set of intermediate PWM signals comprises timing generation of active segments of the second PWM cycle for each intermediate PWM signal of the second set based on the second value.
7. The method of claim 1, further comprising:
sampling, at the PWM signal generator, a PWM cycle of the input PWM signal to determine a value representative of a duty ratio of the PWM cycle; and
wherein generating the multiple output PWM signals comprises timing the multiple output PWM signals based on the value.
8. In a pulse width modulation (PWM) signal generator receiving an input PWM signal and outputting a plurality of output PWM signals synchronized to a synchronization signal, each output PWM signal phase-shifted in relation to the other output PWM signals, a method comprising:
initiating generation of a first PWM cycle for a leading output PWM signal of the plurality of output PWM signals at a first time;
prematurely terminating generation of the first PWM cycle for the leading output PWM signal in response to a synchronization event represented by the synchronization signal at a second time following the first time;
replicating that portion of the first PWM cycle for the leading output PWM signal generated prior to the second time for a first PWM cycle of each non-leading output PWM signal of the plurality of output PWM signals, the first PWM cycle of each non-leading output PWM signal corresponding to the first PWM cycle of the leading output PWM signal;
generating a second PWM cycle for the leading output PWM signal in response to the synchronization event; and
generating a second PWM cycle for each non-leading output PWM signal in response to the synchronization event, the second PWM cycle of each non-leading output PWM signal corresponding to the second PWM cycle of the leading output PWM signal.
9. The method of claim 8, further comprising:
controlling a plurality of light emitting diode (LED) strings using the plurality of output PWM signals.
10. The method of claim 8, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
11. A system comprising:
a pulse width modulation (PWM) signal generator comprising an input to receive an input PWM signal and outputs to provide multiple output PWM signals, the PWM signal generator to generate the multiple output PWM signals having substantially equal duty ratios and that are synchronized to a synchronization signal and having predetermined phase-shifts in relation to each other, and such that a PWM cycle of a leading output PWM signal of the multiple output PWM signals is prematurely terminated in response to a synchronization event represented by the synchronization signal so as to result in a prematurely-terminated PWM cycle for the leading output PWM signal and such that the prematurely-terminated PWM cycle is replicated for each of the non-leading output PWM signals of the multiple output PWM signals while maintaining the predetermined phase-shifts between the multiple output PWM signals.
12. The system of claim 11, further comprising:
a display comprising a plurality of light emitting diode (LED) strings and a plurality of current regulators, each current regulator to regulate a current through a corresponding LED string using a corresponding output PWM signal of the multiple output PWM signals.
13. The system of claim 11, wherein the synchronization signal is a video frame synchronization signal and wherein the synchronization event comprises an assertion of the video frame synchronization signal.
14. The system of claim 11, wherein the PWM cycle comprises a first PWM cycle and wherein the PWM signal generator is to generate the multiple output PWM signals by: initiating generation of the first PWM cycle for a first set of intermediate PWM signals at a first signal generation unit of the PWM signal generator, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; prematurely terminating generation of the first PWM cycle for a leading intermediate PWM signal of the first set in response to the synchronization event; replicating a completed portion of the first PWM cycle for the leading intermediate PWM signal for the first PWM cycle of each non-leading intermediate PWM signal of the first set; generating a second PWM cycle for a second set of intermediate PWM signals at a second signal generation unit of the PWM signal generator in response to the synchronization event, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and combining each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set to generate the multiple output PWM signals.
15. The system of claim 14, wherein the PWM signal generator further is to generate a third PWM cycle for a third set of intermediate PWM signals at a third signal generation unit of the PWM signal generator in response to a completion of the second PWM cycle, and wherein the PWM signal generator is to combine each intermediate PWM signal of the first set with a corresponding intermediate PWM signal of the second set and a corresponding intermediate PWM signal of the third set to generate the multiple output PWM signals.
16. The system of claim 14, wherein:
the PWM signal generator comprises a sampling module, the sampling module to sample a first PWM cycle of the input PWM signal to determine a first value representative of a duty ratio of the first PWM cycle of the input PWM signal and sample a second PWM cycle of the input PWM signal following the first PWM cycle of the input PWM signal to determine a second value representative of a duty ratio of the second PWM cycle of the input PWM signal; and
the PWM signal generator is to initiate generation of the first PWM cycle for the first set of intermediate PWM signals by timing generation of active segments of the first PWM cycle for each intermediate PWM signal of the first set based on the first value, and the PWM signal generator is to generate the second PWM cycle for the second set of intermediate PWM signals by timing generation of active segments of the second PWM cycle for each intermediate PWM signal of the second set based on the second value.
17. The system of claim 11, wherein:
the PWM signal generator further comprises a sampling module to sample a PWM cycle of the input PWM signal to determine a value representative of a duty ratio of the PWM cycle; and
the PWM signal generator is to generate the multiple output PWM signals by timing the multiple output PWM signals based on the value.
18. The system of claim 11, wherein the PWM signal generator comprises:
a first signal generation unit to generate a first set of intermediate PWM signals based on a first count value of a first counter, the first set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
a second signal generation unit to generate a second set of intermediate PWM signals based on a second count value of a second counter, the second set of intermediate PWM signals having the predetermined phase-shifts in relation to each other;
a third signal generation unit to generate a third set of intermediate PWM signals based on a third count value of a third counter, the third set of intermediate PWM signals having the predetermined phase-shifts in relation to each other; and
a signal combination module to combine the first set of intermediate PWM signals, the second set of intermediate PWM signals, and the third set of intermediate PWM signals to generate the multiple output PWM signals.
19. The system of claim 18, wherein:
the first signal generation unit is to initiate generation of a PWM cycle for the first set of intermediate PWM signals responsive to an assertion of a first signal and the first signal generation unit is to assert a second signal responsive to completing generation of the PWM cycle for the first set;
the second signal generation unit is to initiate generation of a PWM cycle for the second set of intermediate PWM signals responsive to the assertion of the second signal and the second signal generation unit is to assert a third signal responsive to completing generation of the PWM cycle for the second set; and
the third signal generation unit is to initiate generation of a PWM cycle for the third set of intermediate PWM signals responsive to the assertion of the third signal and the third signal generation unit is to assert the first signal responsive to completing generation of the PWM cycle for the third set.
20. The system of claim 18, wherein the signal combination module comprises:
a first OR gate having a first input to receive a first intermediate PWM signal of the first set, a second input to receive a first intermediate PWM signal of the second set, and a third input to receive a first intermediate PWM signal of the third set, and an output to provide a first output PWM signal of the multiple output PWM signals; and
a second OR gate having a first input to receive a second intermediate PWM signal of the first set, a second input to receive a second intermediate PWM signal of the second set, and a third input to receive a second intermediate PWM signal of the third set, and an output to provide a second output PWM signal of the multiple output PWM signals.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data processing apparatus switchable between a power saving mode and a normal operating mode, comprising:
a transition triggering event determining section for determining a transition triggering event that causes the data processing apparatus to shift from the power saving mode to the normal operating mode;
a transition triggering event holding section for storing the transition triggering event determined by the transition triggering event determining section;
a mode switching section for causing the data processing apparatus to switch between the power saving mode and the normal operating mode in accordance with the determination by the transition triggering event determining section;
an execution priority determining section for determining, based on the transition triggering event, an execution priority level andor an order of precedence in which a plurality of programs are executed during the normal operating mode; and
a program controlling section for executing the plurality of programs in accordance with the determination by the priority determining section.
2. The data processing apparatus according to claim 1 further comprising:
a document reader;
a document detector for detecting a document that should be read by the document reader;
wherein the transition triggering event is detection of the document by the document detector.
3. The data processing apparatus according to claim 2, wherein the priority determining section sets execution priority levels of programs executed when the document reader reads the document so that the execution priority levels are higher andor the order in which the programs are executed is increased.
4. The data processing apparatus according to claim 1 further comprising an authenticating section for authenticating a user of the data processing apparatus;
wherein the transition triggering event is authentication of the user.
5. The data processing apparatus according to claim 4, wherein the priority determining section sets, based on authentication by the authenticating section, execution priority levels of programs that the user is permitted to use so that the execution priority levels are higher andor the order in which the programs are executed is increased.
6. The data processing apparatus according to claims 1 further comprising a main controller to which a first power supply is supplied only when the data processing apparatus is in the normal operating mode, and a sub controller (200) to which a second power supply is supplied when the data processing apparatus is in the normal operating mode and when the data processing apparatus is in the power saving mode.
7. The data processing apparatus according to claims 1, wherein when the plurality of programs are executed concurrently, a time for which each one of the plurality of programs is executed increases with increasing a value of the execution priority level.
8. An image processing apparatus switchable between a power saving mode and a normal operating mode, comprising:
a transition triggering event determining section for determining a transition triggering event that causes the image processing apparatus to shift from the power saving mode to the normal operating mode;
a transition triggering event holding section for storing the transition triggering event determined by the transition triggering event determining section;
a mode switching section for causing the image processing apparatus to shift from the power saving mode to the normal operating mode in accordance with the determination by the transition triggering event determining section;
an execution priority determining section for determining, based on the transition triggering event, an execution priority level andor an order of precedence in which a plurality of programs are executed during the normal operating mode; and
a program controlling section for executing the plurality of programs in accordance with the determination by the priority determining section.
9. The image processing apparatus according to claim 8 further comprising:
a document reader);
a document detector for detecting a document that should be read by the document reader;
wherein the transition triggering event is detection of the document by the document detector.
10. The image processing apparatus according to claim 9, wherein the priority determining section sets execution priority levels of programs executed when the document reader reads the document so that the execution priority levels are higher andor the order in which the programs are executed is increased.
11. The image processing apparatus according to claim 8 further comprising an authenticating section for authenticating a user of the image processing apparatus;
wherein the transition triggering event is authentication of the user.
12. The image processing apparatus according to claim 11, wherein the priority determining section sets, based on authentication by the authenticating section, execution priority levels of programs that the user is permitted to use so that the execution priority levels are higher andor the order in which the programs are executed is increased.
13. A method for processing data, comprising:
determining a transition triggering event upon which a data processing apparatus shifts from a power saving mode to a normal operating mode, and then holding the transition triggering event;
shifting the data processing apparatus from the power saving mode to the normal operating mode in accordance with the transition triggering event;
determining execution priority levels of a plurality of programs executed when the data processing apparatus is in the normal operating mode andor an order of precedence in which the plurality of programs are executed; and
performing execution of the plurality of programs in accordance with the execution priority levels.
14. The method according to claim 13, wherein the transition triggering event is detection of a document placed on a document reader.
15. The method according to claim 14, wherein the determining is performed such that programs involved in reading the document are given higher execution priority levels andor or higher order of precedence.
16. The method according to claim 13, wherein the transition triggering event is a request for user authentication.
17. The method according to claim 16, wherein the determining is performed such that programs involved in reading the document are given higher execution priority levels andor or higher order of precedence.
18. The method according to claim 13, further comprising supplying electric power to a main controller only when the data processing apparatus is in the normal operating mode and to a sub controller when the data processing apparatus is in the power saving mode and in the normal operating mode.
19. The method according to claim 13, wherein programs having higher execution priority levels are executed longer time when the plurality of programs are concurrently executed.