Author: claimsbot

1-16. (Canceled)
17. A transistor comprising:
an epitaxial layer on the semiconductor substrate;
a dopant source dopant source layer on the epitaxial layer; and
dopant from the dopant source layer distributed within the epitaxial layer to form at least a portion of an extrinsic base for the transistor within the epitaxial layer, a first surface of said portion of the extrinsic base being in direct mechanical contact with the dopant source layer, said portion of the extrinsic base being disposed between the dopant source layer and an intrinsic base for the transistor, said intrinsic base being totally within the epitaxial layer, a second surface of said portion of the extrinsic base being in direct mechanical contact with the intrinsic base, said second surface being opposite said first surface and not contacting said first surface.
18. The transistor of claim 17, wherein the dopant source layer comprises a doped single crystal layer formed on the epitaxial layer.
19. The transistor of claim 17, wherein the epitaxial layer comprises a silicon germanium layer.
20. The transistor of claim 17, the dopant source layer is doped between 51019 and 11021 atomscm3.
21. The transistor of claim 17, wherein the dopant source layer comprises a raised portion of the extrinsic base that is coupled to the dopants diffused from the dopant source layer.
22. The transistor of claim 17, further comprising a pedestal on the epitaxial layer, wherein the dopant source layer is formed around the pedestal such that the pedestal defines a portion of the epitaxial layer in which the dopant source layer is not formed on the epitaxial layer.
23. The transistor of claim 22, wherein the pedestal further defines an emitter opening.
24. The transistor of claim 17, further comprising the steps of:
a subcollector within the semiconductor substrate; and
a pedestal implant within the semiconductor substrate, wherein the pedestal implant has a first surface and an opposing second surface, wherein the first surface of the pedestal implant is in direct mechanical contact with the subcollector, wherein the second surface of the pedestal implant is in direct mechanical contact with the intrinsic base, and wherein the pedestal implant is not in direct mechanical contact with said portion of the extrinsic base.
25. The transistor of claim 24, further comprising a deep trench isolation at the edges of the subcollector, said deep trench isolation surrounding the subcollector and electrically isolating the subcollector.
26. A transistor, comprising:
an epitaxial layer on a semiconductor substrate;
a dopant source layer on a first portion of the epitaxial layer;
an emitter material on a second portion of the epitaxial layer, said second portion of the epitaxial layer being adjacent to said first portion of the epitaxial layer;
dopant from the dopant source layer within the epitaxial layer to form at least a portion of an extrinsic base for the transistor within the epitaxial layer, said portion of the extrinsic base being in direct mechanical contact with the dopant source layer, a first surface of said portion of the extrinsic base being disposed between the dopant source layer and an intrinsic base for the transistor, said intrinsic base being totally within the epitaxial layer, a second surface of said portion of the extrinsic base being in direct mechanical contact with the intrinsic base, said second surface being opposite said first surface and not contacting said first surface; and
emitter dopant from the emitter material within said second portion of the epitaxial layer, said emitter dopant forming an emitter for the transistor, said emitter being totally within the epitaxial layer, said emitter being surrounded by said portion of the extrinsic base.
27. The transistor of claim 26, further comprising:
a cap layer on the dopant source layer; and
a spacer layer on the cap layer,
wherein a first surface of the spacer layer is in direct mechanical contact with a surface of the emitter material,
wherein a second surface of the spacer layer is in direct mechanical contact with a first surface of the cap layer,
wherein a second surface of the cap layer is in direct mechanical contact with a surface of the dopant source layer, and
wherein the surface of the emitter material, the first surface of the spacer layer, the second surface of the spacer layer, the first surface of the cap layer, the second surface of the cap layer, and the surface of the dopant source layer are about parallel.
28. The transistor of claim 26, further comprising:
a subcollector within the semiconductor substrate; and
a pedestal implant within the semiconductor substrate, wherein the pedestal implant has a first surface and an opposing second surface, wherein the first surface of the pedestal implant is in direct mechanical contact with the subcollector, wherein the second surface of the pedestal implant is in direct mechanical contact with the intrinsic base, and wherein the pedestal implant is not in direct mechanical contact with said portion of the extrinsic base.
29. The transistor of claim 28, further comprising a trench isolation at the edges of the subcollector, said deep trench isolation surrounding the subcollector and electrically isolating the subcollector.
30. A transistor, comprising:
semiconductor substrate;
epitaxial layer on the substrate;
a dopant source layer on the epitaxial layer;
dopant from the dopant source layer distributed within the epitaxial layer to form a first portion of an extrinsic base for the transistor within the epitaxial layer, said first portion of the extrinsic base being in direct mechanical contact with the dopant source layer, said first portion of the extrinsic base being disposed between the dopant source layer and an intrinsic base for the transistor, said intrinsic base being totally within the epitaxial layer; and
a pedestal on the epitaxial layer, wherein the dopant source layer is formed around the pedestal such that the pedestal defines a portion of the epitaxial layer in which the dopant source layer is not formed on the epitaxial layer, wherein the pedestal comprises a high pressure oxide layer, a nitride layer above the high pressure oxide layer, and an oxide layer above the nitride layer, and patterning the high pressure oxide layer, nitride layer and oxide layer, and wherein the dopant source layer does not exist above the high pressure oxide layer.
31. The transistor of claim 30, wherein the dopant source layer comprises a raised portion of the extrinsic base.
32. The transistor of claim 30, wherein the pedestal defines an emitter region of the epitaxial layer.
33. The transistor of claim 30, further comprising a second portion of the extrinsic base distributed within epitaxial layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A wiring substrate for an electronic-component inspection apparatus comprising:
a substrate body composed of a plurality of stacked ceramic layers, said substrate body having a front surface and a back surface; and
front-surface terminal electrodes formed on the front surface of the substrate body, and grouped into unit inspection patterns, individual ones of the unit inspection patterns being constituted by a plurality of the front-surface terminal electrodes disposed so as to correspond to a plurality of terminal electrodes of individual electronic components to be inspected,
wherein said unit inspection patterns are disposed so as to be offset distance-wise from a lattice arrangement in at least one of orthogonal first and second directions, as viewed from above the front surface of the substrate body.
2. A wiring substrate for an electronic-component inspection apparatus comprising:
a substrate body composed of a plurality of stacked ceramic layers, said substrate body having a front surface and a back surface; and
front-surface terminal electrodes formed on the front surface of the substrate body, and grouped into unit inspection patterns, individual ones of the unit inspection patterns being constituted by a plurality of the front-surface terminal electrodes disposed so as to correspond to a plurality of terminal electrodes of individual electronic components to be inspected,
wherein said unit inspection patterns are disposed so as to be offset distance-wise from a lattice arrangement of rows and columns in at least one of orthogonal first and second directions, as viewed from above the front surface of the substrate body, wherein the unit inspection patterns are arranged in every other row but not in alternate rows in at least one of the first and second directions.
3. A wiring substrate for an electronic-component inspection apparatus comprising:
a substrate body composed of a plurality of stacked ceramic layers, said substrate body having a front surface and a back surface; and
front-surface terminal electrodes formed on the front surface of the substrate body, and grouped into unit inspection patterns, individual ones of the unit inspection patterns being constituted by a plurality of the front-surface terminal electrodes disposed so as to correspond to a plurality of terminal electrodes of individual electronic components to be inspected,
wherein said unit inspection patterns are regularly arranged in orthogonal first and second directions, as viewed from above the front surface of the substrate body, such that centroids of the respective unit inspection patterns coincide with alternate ones of intersections between first imaginary lines and second imaginary lines extending along the first and second directions, respectively, and passing through the centroids of the unit inspection patterns.
4. The wiring substrate for an electronic-component inspection apparatus according to claim 1, wherein some of the front-surface terminal electrodes each includes at least an inspection pad formed inside an associated unit inspection pattern, a cover pad connected to a via conductor exposed to the front surface of the substrate body, and a connection wiring trace which connects the inspection pad and the cover pad.
5. The wiring substrate for an electronic-component inspection apparatus according to claim 2, wherein some of the front-surface terminal electrodes each includes at least an inspection pad formed inside an associated unit inspection pattern, a cover pad connected to a via conductor exposed to the front surface of the substrate body, and a connection wiring trace which connects the inspection pad and the cover pad.
6. The wiring substrate for an electronic-component inspection apparatus according to claim 3, wherein some of the front-surface terminal electrodes each includes at least an inspection pad formed inside an associated unit inspection pattern, a cover pad connected to a via conductor exposed to the front surface of the substrate body, and a connection wiring trace which connects the inspection pad and the cover pad.
7. The wiring substrate for an electronic-component inspection apparatus according to claim 4, wherein individual ones of the unit inspection patterns have a rectangular shape as viewed from above the front surface of the substrate body; a plurality of inspection pads are formed along all sides of respective unit inspection patterns; cover pads individually connected to the inspection pads via dedicated connection wiring traces are formed in an area surrounded by the inspection pads associated with an unit inspection pattern or outside an associated unit inspection pattern; and the cover pads are connected to via conductors which pass through at least an uppermost ceramic layer which forms the front surface of the substrate body.
8. The wiring substrate for an electronic-component inspection apparatus according to claim 5, wherein individual ones of the unit inspection patterns have a rectangular shape as viewed from above the front surface of the substrate body; a plurality of inspection pads are formed along all sides of respective unit inspection patterns; cover pads individually connected to the inspection pads via dedicated connection wiring traces are formed in an area surrounded by the inspection pads associated with an unit inspection pattern or outside an associated unit inspection pattern; and the cover pads are connected to via conductors which pass through at least an uppermost ceramic layer which forms the front surface of the substrate body.
9. The wiring substrate for an electronic-component inspection apparatus according to claim 6, wherein individual ones of the unit inspection patterns have a rectangular shape as viewed from above the front surface of the substrate body; a plurality of inspection pads are formed along all sides of respective unit inspection patterns; cover pads individually connected to the inspection pads via dedicated connection wiring traces are formed in an area surrounded by the inspection pads associated with an unit inspection pattern or outside an associated unit inspection pattern; and the cover pads are connected to via conductors which pass through at least an uppermost ceramic layer which forms the front surface of the substrate body.
10. The wiring substrate for an electronic-component inspection apparatus according to claim 4, wherein the cover pads are larger than the inspection pads.
11. The wiring substrate for an electronic-component inspection apparatus according to claim 5, wherein the cover pads are larger than the inspection pads.
12. The wiring substrate for an electronic-component inspection apparatus according to claim 6, wherein the cover pads are larger than the inspection pads.
13. The wiring substrate for an electronic-component inspection apparatus according to claim 4, wherein the cover pads are larger in diameter than the via conductors to which the cover pads are connected.
14. The wiring substrate for an electronic-component inspection apparatus according to claim 5, wherein the cover pads are larger in diameter than the via conductors to which the cover pads are connected.
15. The wiring substrate for an electronic-component inspection apparatus according to claim 6, wherein the cover pads are larger in diameter than the via conductors to which the cover pads are connected.
16. The wiring substrate for an electronic-component inspection apparatus according to claim 4, wherein the diameter of the cover pads is at least 2.5 times the diameter of the via conductors.
17. The wiring substrate for an electronic-component inspection apparatus according to claim 5, wherein the diameter of the cover pads is at least 2.5 times the diameter of the via conductors.
18. The wiring substrate for an electronic-component inspection apparatus according to claim 6, wherein the diameter of the cover pads is at least 2.5 times the diameter of the via conductors.

1. A computer-implemented method of automatically detecting a face in an image, said method comprising:
generating an integral image based upon said image;
sub-sampling said integral image to generate a plurality of sub-sampled integral images, wherein said plurality of sub-sampled integral images comprises a plurality of regions;
applying a plurality of classifiers to a region of said plurality of regions of said plurality of sub-sampled integral images to generate classification data; and
determining whether said region is associated with a face based upon said classification data,
wherein said plurality of sub-sampled integral images comprise different scales of said integral image.
2. The method of claim 1 further comprising:
applying a plurality of classifiers to a second region of said plurality of regions of said plurality of sub-sampled integral images to generate second classification data;
determining whether said second region is associated with a face based upon said second classification data; and
wherein said region and said second region are associated with localized data of said plurality of sub-sampled integral images, and wherein said applying a plurality of classifiers to said region and said applying a plurality of classifiers to said second region involve localized data processing.
3. The method of claim 1 further comprising:
generating a second image from said image based upon results of determining that said region is associated with said face.
4. The method of claim 3, wherein said second image comprises graphical data for rendering a graphical object around said face, and wherein said graphical object is selected from a group consisting of a box, a circle, a polygon, and a pair of brackets.
5. The method of claim 1, wherein said applying a plurality of classifiers further comprises:
applying a first plurality of classifiers in a first stage to said region of said plurality of sub-sampled integral images to generate first classification data; and
if said region is determined to be associated with said face based upon said first classification data, applying a second plurality of classifiers in a second stage to said region of said plurality of sub-sampled integral images to generate second classification data.
6. The method of claim 5, wherein said determining whether said region is associated with a face further comprises determining said region is associated with said face if said region is determined to be associated with said face based upon said second classification data.
7. The method of claim 1, wherein said plurality of classifiers comprises at least two classifiers with a different characteristic, wherein said different characteristic is selected from a group consisting of a size and a shape.
8. The method of claim 1, wherein said determining whether said region is associated with a face further comprises:
comparing a first portion of said classification data with a predetermined threshold to determine that a region of said image is associated with a portion of said face, wherein said first portion of said classification data is associated with said region of said image.
9. A non-transitory computer-usable medium having computer-readable program code embodied therein for causing a computer system to perform a method of automatically detecting a face in an image, said method comprising:
generating an integral image based upon said image;
sub-sampling said integral image to generate a plurality of sub-sampled integral images, wherein said plurality of sub-sampled integral images comprises a plurality of regions;
applying a plurality of classifiers to a region of said plurality of regions of said plurality of sub-sampled integral images to generate classification data; and
determining whether said region is associated with a face based upon said classification data.
10. The non-transitory computer-usable medium of claim 9, wherein said method further comprises:
generating a second image from said image based upon results of determining that said region is associated with said face.
11. The non-transitory computer-usable medium of claim 10, wherein said second image comprises graphical data for rendering a graphical object around said face, and wherein said graphical object is selected from a group consisting of a box, a circle, a polygon, and a pair of brackets.
12. The non-transitory computer-usable medium of claim 9, wherein said applying a plurality of classifiers further comprises:
applying a first plurality of classifiers in a first stage to said region of said plurality of sub-sampled integral images to generate first classification data; and
if said region is determined to be associated with said face based upon said first classification data, applying a second plurality of classifiers in a second stage to said region of said plurality of sub-sampled integral images to generate second classification data.
13. The non-transitory computer-usable medium of claim 12, wherein said determining whether said region is associated with a face further comprises determining said region is associated with said face if said region is determined to be associated with said face based upon said second classification data.
14. The non-transitory computer-usable medium of claim 9, wherein said plurality of classifiers comprises at least two classifiers with a different characteristic, wherein said different characteristic is selected from a group consisting of a size and a shape.
15. The non-transitory computer-usable medium of claim 9, wherein said determining whether said region is associated with a face further comprises:
comparing a first portion of said classification data with a predetermined threshold to determine that a region of said image is associated with a portion of said face, wherein said first portion of said classification data is associated with said region of said image.
16. A computer system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor perform a method of detecting a face in an image, said method comprising:
generating an integral image based upon said image;
sub-sampling said integral image to generate a plurality of sub-sampled integral images, wherein said plurality of sub-sampled integral images comprises a plurality of regions;
applying a plurality of classifiers to a region of said plurality of regions of said plurality of sub-sampled integral images to generate classification data; and
determining whether said region is associated with a face based upon said classification data.
17. The computer system of claim 16, wherein said method further comprises:
generating a second image from said image based upon results of determining that said region is associated with said face.
18. The computer system of claim 17, wherein said second image comprises graphical data for rendering a graphical object around said face, and wherein said graphical object is selected from a group consisting of a box, a circle, a polygon, and a pair of brackets.
19. The computer system of claim 16, wherein said applying a plurality of classifiers further comprises:
applying a first plurality of classifiers in a first stage to said region of said plurality of sub-sampled integral images to generate first classification data; and
if said region is determined to be associated with said face based upon said first classification data, applying a second plurality of classifiers in a second stage to said region of said plurality of sub-sampled integral images to generate second classification data.
20. The computer system of claim 19, wherein said determining whether said region is associated with a face further comprises determining said region is associated with said face if said region is determined to be associated with said face based upon said second classification data.
21. The computer-usable medium of claim 16, wherein said plurality of classifiers comprises at least two classifiers with a different characteristic, wherein said different characteristic is selected from a group consisting of a size and a shape.
22. The computer system of claim 16, wherein said determining whether said region is associated with a face further comprises:
comparing a first portion of said classification data with a predetermined threshold to determine that a region of said image is associated with a portion of said face, wherein said first portion of said classification data is associated with said region of said image.
23. The computer system of claim 16, wherein said processor comprises a graphics processing unit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of biosensor-based detection of toxins, comprising the steps of:
concentrating a plurality photosynthetic organisms in a fluid to be analyzed into a concentrated region using biased AC electro-osmosis;
obtaining a measured photosynthetic activity of said photosynthetic organisms in said concentrated region, wherein chemical, biological or radiological agents reduce a nominal photosynthetic activity of said photosynthetic organisms, and
determining a presence of at least one of said chemical, biological or radiological agents, or precursors thereof, in said fluid based on said measured photosynthetic activity.
2. The method of claim 1, wherein said plurality of photosynthetic organisms are naturally-occurring, free-living, indigenous organisms in said fluid.
3. The method of claim 1, wherein said photosynthetic activity comprises chlorophyll fluorescence induction.
4. The method of claim 1, wherein a lab-on-a-chip system is used for said concentrating step.
5. The method of claim 1, wherein said fluid is drawn from a source of primary-source drinking water.
6. The method of claim 5, further comprising the step of refreshing a supply of said photosynthetic organisms by drawing a fresh supply of said drinking water and repeating said method.
7. The method of claim 1, wherein said determining step further comprises the steps of:
providing at least one time-dependent control signal generated by said photosynthetic organism is said fluid;
obtaining a time-dependent biosensor signal from said biosensor in said fluid for the presence of one or more of said agents;
processing said time-dependent biosensor signal to obtain a plurality of feature vectors using at least one of amplitude statistics and a time-frequency analysis, and
determining said presence of at least one of said chemical, biological or radiological agents, or precursors thereof, from said feature vectors based on reference to said control signal.
8. The method of claim 7, wherein said time-frequency analysis comprises wavelet coefficient analysis.
9. The method of claim 7, wherein both said amplitude statistics and time-frequency analysis are used in said processing step.
10. The method of claim 7, further comprising the step of identifying which of said agents are present in said fluid.
11. The method of claim 10, wherein a linear discriminant method is used for said identifying step.
12. The method of claim 11, wherein said linear discriminant method comprises support vector machine (SVM) classification.
13. The method of claim 1, wherein a DC bias for said biased ACEO is from 1 to 10 volts.