Author: claimsbot

1. An information handling system comprising:
a processing system configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system;
a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system;
a chipset including a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system;
a first subgroup of power rails configured to be enabled during use of the processing system to power the shared resource and the non-shared resource of the processing system; and
a second subgroup of power rails configured to be enabled during use of the low-power processing system to power the shared resource of the processing system, and to further power a shared resource and a non-shared resource of the low-power processing system.
2. The information handling system of claim 1, further comprising a low-power processing module including a low power processor of the low-power processing system, wherein the low-power processing module is accessible to the chipset during operation of the processing system.
3. The information handling system of claim 1, further comprising:
wherein the chipset includes the low-power processing system;
wherein the power system is operable to enable the processing system separate from the low-power processing system; and
wherein the power system is further operable to enable the low-power processing system separate from the processing system.
4. The information handling system of claim 1, further comprising:
a low-power processing module externally coupled to the chipset;
a video processing resource within the chipset and accessible to the processing system during operation of the processing system;
wherein the video processing resource is accessible to the low-power processing module during operation of the low-power processing system and a reduced operating state of the processing system;
a power subsystem of the power system configured to enable a portion of the chipset; and
wherein the low-power processing system is configured to access the enabled portion of the chipset to output video using the shared resource of the processing system during the reduced operating state of the processing system.
5. The information handling system of claim 1, further comprising:
a video input source operably coupled to the chipset during operation of the low-power processing system;
a video output resource of the processing system configured to identify the video input source; and
wherein the video output resource is configured to process a video input from the video input source to a display format of the display.
6. The information handling system of claim 1, wherein the power system is further configured to enable a power rail of the first group of power rails and a power rail of a the second group of power rails based on an operating state of the processing system and operating state of the low-power processing system.
7. The information handling system of claim 1, further comprising:
wherein the chipset includes a low power processor of the low-power processing system; and
a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of the processor and the low power processor.
8. The information handling system of claim 3, further comprising:
a video processing resource within the chipset and accessible to the processing system during operation of the processing system; and
wherein the video processing resource is accessible to the low-power processing system during operation of the low-power processing system.
9. The information handling system of claim 8, wherein the video processing resource includes:
a video raster coupled to the chipset and operable to be accessed as a shared video output resource; and
wherein the video raster is further accessible to the low-power processing system and the processing system to simultaneously output video of the low-power processing system and video of the processing system to a shared video display resource.
10. The information handling system of claim 5, further comprising a power subsystem configured to enable the video output resource.
11. A chipset comprising:
a processor configured to access a shared resource of a processing system during operation of the processing system;
a power system configured to enable a powering of the shared resource during operation of the processing system and operation of a low-power processing system;
a low power processor of the low-power processing system, wherein the low power processor is configured to be enabled during a reduced operation of the processor; and
a low power processor subsystem power source configured to be enabled in response to enabling the low power processor separate from the processing system.
12. The chipset of claim 11, further comprising a peripheral switching module configured to couple an output to the shared resource during use of processing system and the low-power processing system.
13. The chipset of claim 11, wherein the processor is a part of the processing system.
14. The chipset of claim 11, further comprising a low power processor of the low-power processing system.
15. The chipset of claim 12, wherein the shared resource includes:
a video display accessible to the low-power processing system during operation of the low-power processing system; and
wherein the video display is accessible to the processing system during operation of the processing system.
16. The chipset of claim 11, further comprising:
a low power processor of the low-power processing system; and
wherein the processor is a part of the processing system.
17. An information handling system comprising:
a processing system configured to access a shared resource and a non-shared resource during operation of the processing system;
a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from operation of the processing system;
a power system configured to power the processing system, the low-power processing system, the shared resource, and the non-shared resource; and
a chipset comprising:
a processor configured to access the shared resource of the processing system during the operation of the processing system;
a low power processor configured to access the shared resource of the processing system during the operation of the low-power processing system; and
a low power processor subsystem power source configured to be enabled in response to enabling the low power processor separate from the processing system.
18. The information handling system of claim 17, further comprising:
a control module operably coupled to the chipset and the power system to initiate powering the shared resource and the non-shared resource; and
a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of processing system and the low-power processing system.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the memory cell array is divided into a plurality of sub-arrays by boundaries which are perpendicular to the extending directions of the memory lines;
a wire channel in each of the sub-arrays is shifted from a wire channel in an adjacent sub-array in the directions of the boundaries;
an array boundary wire channel is provided along the boundaries between the adjacent sub-arrays; and
the signal line extends through a wire channel in each of the sub-arrays and the array boundary wire channel.
2. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers at least one of the bit lines, and a wire channel is formed between the lower-layer dummy wire patterns so as to extend in the direction of the bit lines; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers at least one of the word lines, and a wire channel is formed between the upper-layer dummy wire patterns so as to extend in the direction of the word lines.
3. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers at least one of the word lines, and a wire channel is formed between the lower-layer dummy wire patterns so as to extend in the direction of the word lines; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers at least one of the bit lines, and a wire channel is formed between the upper-layer dummy wire patterns so as to extend in the direction of the bit lines.
4. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
first and second memory cell arrays are provided on the same chip, each of the first and second memory cell arrays including a plurality of word lines and a plurality of bit lines, the bit lines crossing the word lines at right angles;
a series of lower-layer wire channels are formed between a plurality of lower-layer dummy wire patterns, the lower-layer wire channels extending in the bit line direction on the first memory cell array, the lower-layer wire channels extending in the word line direction on the second memory cell array;
a series of upper-layer wire channels are formed between a plurality of upper-layer dummy wire patterns, the upper-layer wire channels on the first memory cell array extending in the word line direction, the upper-layer wire channels on the second memory cell array extending in the word line direction; and
the signal line extends over the first and second memory cell arrays through the lower-layer wire channels or the upper-layer wire channels.
5. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers four or more of a plurality of intersection points of the word lines and the bit lines, and a wire channel is formed between the lower-layer dummy wire patterns to have a lattice shape; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers four or more of a plurality of intersection points of the word lines and the bit lines in a combination different from that of the lower-layer dummy wire patterns, and a wire channel having a lattice shape is formed between the upper-layer dummy wire patterns.
6. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of wiring-prohibited regions formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the wiring-prohibited regions, wherein:
the signal line is a metal line formed in the same layer which includes the wiring-prohibited regions and a route; and
a route of the signal line is determined using an automatic wiring tool.

1. A piezoelectric actuator for driving a lens unit along an optical axis, comprising:
a fixed member;
a movable member movably received in the fixed member, the movable member comprising a contacting portion positioned thereon;
a magnetic plate fixed on the fixed member;
a magnet fixed on the movable, the magnet being aligned with the magnetic plate along a direction substantially perpendicular to the optical axis;
a piezoelectric member fixed on the fixed member and contacting on the contacting portion of the movable member, the piezoelectric be configured for driving the movable member to move along the optical axis; and
a circuit board configured for providing voltages to the piezoelectric member.
2. The piezoelectric actuator of claim 1, further comprising a bottom plate fixed on the fixed member for restricting the movable member in the fixed member.
3. The piezoelectric actuator of claim 2, wherein the fixed member further comprises a plurality of fixing holes in an end surface thereof facing toward the bottom plate, the bottom plate comprises a plurality of fixing poles spatially corresponding to the fixing holes, each fixed pole inserts into a corresponding fixing hole.
4. The piezoelectric actuator of claim 2, wherein the bottom plate defines a central opening therein for allowing light from the lens unit to pass therethrough.
5. The piezoelectric actuator of claim 2, further comprising a guiding member for guiding the movable member to move along the optical axis, the guiding member slidably passing through the movable member, and two opposite ends of the guiding member being respectively fixed on the fixed member and the bottom plate.
6. The piezoelectric actuator of claim 5, wherein the movable member comprises a yoke portion positioned on a corner thereof, and the guiding member is slidably mounted on the yoke portion.
7. The piezoelectric actuator of claim 1, wherein the fixed member defines a mounting opening in a sidewall thereof, the piezoelectric member is fixedly received in the mounting opening.
8. The piezoelectric actuator of claim 7, wherein the fixed member defines a first groove in the sidewall near the mounting opening, the magnetic plate is fixedly received in the first groove.
9. The piezoelectric actuator of claim 1, wherein the fixed member defines a first receiving space through two opposite ends thereof along the optical axis, the movable member is movably received in the first receiving space.
10. The piezoelectric actuator of claim 1, wherein the movable member defines a second groove in a sidewall thereof, the magnet is fixedly received in the second groove.
11. The piezoelectric actuator of claim 10, wherein the movable member defines a receiving portion in the sidewall, the contacting portion is fixed in the receiving portion.
12. The piezoelectric actuator of claim 1, wherein the contacting portion is integrally formed with the movable member.
13. The piezoelectric actuator of claim 1, further comprising a restricting sheet for restricting the piezoelectric member and the magnetic plate on the fixed member, the restricting member being fixed on a sidewall of the fixed member with the piezoelectric member and the magnetic plate fixed on.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacture of titanium alloy for use in a high temperature and high stress environment, comprising:
providing a titanium alloy consisting essentially of, in weight %, 0.2 to 0.5 iron, 0.02 to 0.12 oxygen, 0.15 to 0.6 silicon and balance titanium and incidental impurities; followed by
performing a first heat treatment of said titanium alloy at a first temperature that is above the temperature where a precipitate phase begins to dissolve and below a temperature where the titanium alloy has a structure that is greater than 50% of a beta phase; followed by
cold rolling said titanium alloy to a desired thickness; followed by
performing a second heat treatment of said titanium alloy at a second temperature that allows precipitation of second phase particles in the titanium alloy; and followed by
performing a third heat treatment of said titanium alloy at a third temperature to recrystallize the titanium alloy without dissolving precipitate particles.
2. The method of claim 1, wherein said first temperature is selected wherein recrystallization and softening of said titanium alloy is optimized without substantial coarsening of second phase particles.
3. The method of claim 1, wherein said first temperature is approximately 1500-1600\xb0 F.
4. The method of claim 1, wherein said rolling of said titanium alloy reduces the thickness of said titanium alloy by at least 65%.
5. The method of claim 1, wherein said second temperature is approximately 900-1100\xb0 F.
6. The method of claim 1, wherein said third temperature is approximately 1200-1600\xb0 F.
7. The method of claim 1, wherein any of said first, second or third heat treatments are performed in an air atmosphere or an inert gas atmosphere.
8. The method of claim 1, further comprising imparting a controlled strain unto said titanium alloy.
9. The method of claim 8, wherein said imparting of a controlled strain unto said titanium alloy involves temper rolling or tension leveling said titanium alloy.
10. A method for manufacture of titanium alloy for use in a high temperature and high stress environment, comprising:
providing a titanium alloy consisting essentially of, in weight %, 0.2 to 0.5 iron, 0.02 to 0.12 oxygen, 0.15 to 0.6 silicon and balance titanium and incidental impurities;
performing a first heat treatment of said titanium alloy at a first temperature that is above the temperature where a precipitate phase begins to dissolve and below a temperature where the titanium alloy has a structure that is greater than 50% of a beta phase; followed by
cold rolling said titanium alloy to a desired thickness; followed by
performing a second heat treatment of said titanium alloy at said first temperature for a first time wherein a grain size between that of ASTM 3 and ASTM 6grade titanium alloys is achieved; and followed by
performing a third heat treatment of said titanium alloy at a second temperature to precipitate silicides to prevent grain growth during use.
11. The method of claim 10, wherein said first temperature is selected wherein recrystallization and softening of said titanium alloy is optimized without substantial coarsening of second phase particles.
12. The method of claim 10, wherein said first temperature is approximately 1500-1600\xb0 F.
13. The method of claim 10, wherein said rolling of said titanium alloy reduces the thickness of said titanium alloy by at least than 65%.
14. The method of claim 10, wherein said first time is approximately 5 minutes to 1 hour.
15. The method of claim 10, wherein said second temperature is approximately 900-1100\xb0 F.
16. The method of claim 10, wherein any of said first, second or third heat treatments are performed in an air atmosphere or an inert gas atmosphere.
17. The method of claim 10, further comprising imparting a controlled strain unto said titanium alloy.
18. The method of claim 17, wherein said imparting of a controlled strain unto said titanium alloy involves temper rolling or tension leveling said titanium alloy.
19. A method for manufacture of titanium alloy for use in a high temperature and high stress environment, comprising:
performing a first heat treatment of said titanium alloy at a first temperature that is below a temperature where the titanium alloy has a structure that is greater than 50% of a beta phase; followed by
cold rolling said titanium alloy to a desired thickness; followed by
performing a second heat treatment of said titanium alloy at a second temperature that allows precipitation of second phase particles in the titanium alloy; and followed by
performing a third heat treatment of said titanium alloy at a third temperature to recrystallize the titanium alloy without dissolving the precipitate.
20. A method for manufacture of titanium alloy for use in a high temperature and high stress environment, comprising:
performing a first heat treatment of said titanium alloy at a first temperature that is below a temperature where the titanium alloy has a structure that is greater than 50% of a beta phase; followed by
cold rolling said titanium alloy to a desired thickness; followed by
performing a second heat treatment of said titanium alloy at said first temperature for a first time wherein a grain size between that of ASTM 3 and ASTM 6 grade

titanium alloys is achieved; and followed by
performing a third heat treatment of said titanium alloy at a second temperature to precipitate silicides to prevent grain growth during use.