Author: claimsbot

1. A method for generating kerf data, comprising the steps of:
submitting chip data for chip processing;
generating kerf data corresponding to the chip data; and
manipulating the kerf data by use of kerf processing using a same manipulation process as for the chip data.
2. The method of claim 1, wherein the generating step provides for a just-in-time kerf build substantially immediately prior to mask manufacturing.
3. The method of claim 2, wherein the generating step provides for a just-in-time kerf build so that multiple versions of kerf design images are avoided.
4. The method of claim 1, further comprising providing a graphical user interface (GUI) to receive at least one of information and parameters prior to the submitting and generating steps and which is made available to the submitting and generating steps.
5. The method of claim 1, further comprising sharing a same mask order information between the submitting and generating steps.
6. The method of claim 5, wherein the sharing mask order information step includes accessing the mask order information from at least one of a file and a database.
7. The method of claim 1, further comprising the step of manipulating the kerf data and the chip data with substantially a same version of design manipulation software.
8. The method of claim 1, further comprising load balancing at least one of the chip design processing and the kerf processing.
9. The method of claim 1, wherein the manipulating step includes producing kerf test structures for wafer testing.
10. The method of claim 1, wherein in the event an error occurs during at least one of the generating and manipulating step, an email is sent to a destination indicating a nature of the error, such that correction of the error can be made while the chip processing is occurring in order to reduce mean time to repair and to reduce cycle time for the kerf processing.
11. The method of claim 10, further including sending the email if validation checks detect an error in the kerf data, in order to reduce mean time to repair the error.
12. The method of claim 1, wherein at least one of the generating step and the manipulating step occurs concurrently with the chip processing.
13. The method of claim 1, wherein the submitting step produces a chip design image and the manipulating step produces a kerf design image such that the produced chip design image and the kerf design image remain consistent.
14. The method of claim 1, further comprising the steps of:
archiving the manipulated kerf data; and
updating processing logs to record information about at least one of the chip and kerf processing for providing an audit process for debugging issues.
15. A method for generating kerf data, the method comprising the steps of:
executing design manipulation utilities for at least chip data design manipulation;
creating a kerf design build utilities file by assembling kerf features previously designed and stored in a library of kerf design data as a result of kerf data manipulation; and
creating and manipulating kerf design data concurrently with chip data design manipulation processing by using same parameters in the kerf design data manipulation and chip data design manipulation thereby ensuring that the kerf design data and the chip design data are consistent.
16. The method of claim 15, wherein in the creating and manipulating step the design data includes one of shrinks, expands and derivation of new data levels.
17. The method of claim 15, wherein in the creating and manipulating step includes processing assist features for device enhancements and addition of nonfunctional shapes for increased manufacturing line process latitude.
18. The method of claim 15, wherein after successful completion of the chip data design manipulation processing, at least one of a chip design image and modified design data is archived in a chip design data repository.
19. The method of claim 15, wherein the creating kerf design data uses information associated with at least one of the chip data and a mask order for the chip, and the information is obtained from a previously created file thereby minimizing user inputs and reducing errors.
20. The method of claim 15, following successful completion of the creating and manipulation step, submitting the kerf design data to validation checks to ensure that the combination of a kerf design grid and a chip design grid prevents grid snapping at the mask write tool.
21. A system for generating kerf data, comprising:
a component to submit chip data for chip processing;
a component to generate kerf data corresponding to the chip data; and
a component to manipulate the kerf data via kerf processing using the same manipulation process as the chip data.
22. The system of claim 21, wherein the component to generate kerf data provides a just-in-time kerf build substantially immediately prior to mask manufacturing and provides a just-in-time kerf build so that multiple versions of kerf design images are avoided.
23. The system of claim 21, further comprising a component to provide a graphical user interface (GUI) to receive at least one of information and parameters which is made available to the component to submit chip data for chip processing and the component to generate kerf data corresponding to the chip data.
24. The system of claim 21, further comprising a means for sharing the same mask order information between all components.
25. The system of claim 21, wherein the chip processing and kerf processing are concurrent, and wherein the chip processing produces a chip design image and the kerf processing produces a kerf design image, the produced chip design image and the kerf design image being consistent.
26. The system of claim 21, further comprising a component to produce kerf test structures for improved reliability of wafer testing.
27. A computer program product comprising a computer usable medium having readable program code embodied in the medium, the computer program product includes:
a first computer program code to submit chip data for chip processing;
a second computer program code to generate kerf data corresponding to the chip data; and
a third computer program code to manipulate the kerf data via kerf processing using the same manipulation process as the chip data.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of manufacturing an integrated circuit, the method comprising:
selecting a programmable logic device to be formed on a chip;
selecting a dedicated device to be formed on the chip;
selecting an interface circuit to be formed on the chip to provide the interface connections between the programmable logic device and the dedicated device; the interface circuit comprising a plurality of interface buffer circuits;
determining a number of input interface connections to the dedicated device from the programmable logic device and a number of output interface connections from the dedicated device to the programmable logic device;
adjusting the routing of the conductors to be formed in a layer of the integrated circuit for a subset of the plurality of interface buffer circuits based on the determined number of at least one of the input interface connections and the output interface interconnects, wherein the subset of the plurality of interface buffer circuits is the same as the remainder of the plurality of interface buffer circuits except for the routing of the conductors.
2. The method of claim 1, wherein adjusting the routing of the conductors comprises selecting a mask based on the determined number of at least one of the input interface connections and the output interface interconnects to form the routing conductors.
3. The method of claim 1, wherein adjusting the routing of the conductors comprises is based on only the output interface interconnections.
4. The method of claim 1, wherein adjusting the routing of the conductors comprises is based on only the input interface interconnections.
5. The method of claim 1, further comprising forming the integrated circuit.
6. An integrated circuit comprising:
a programmable logic device;
a dedicated device; and
an interface coupled between the programmable logic device and the dedicated device, the interface comprising a plurality of programmable buffer circuits, each programmable buffer circuit comprising:
a first tri-statable buffer having an input terminal coupled to the programmable logic device, a control terminal to turn the first tri-statable buffer on or off, and an output terminal coupled to the dedicated device; and
a second tri-statable buffer having an input terminal coupled to the output terminal of the first tri-statable buffer, a control terminal to turn the second tri-statable buffer on or off, and an output terminal coupled to the input terminal of the first tri-statable buffer;
wherein the plurality of programmable buffer circuits are programmable by one or more programmable elements coupled to the control terminal of the first tri-statable buffer and the control terminal of the second tri-statable buffer.
7. An integrated circuit comprising:
a programmable logic device;
a dedicated device; and
an interface coupled between the programmable logic device and the dedicated device, the interface comprising a plurality of programmable buffer circuits, each programmable buffer circuit comprising:
a first tri-statable buffer having an input terminal coupled to the programmable logic device, a control terminal to turn the first tri-statable buffer on or off, and an output terminal coupled to the dedicated device; and
a second tri-statable buffer having an input terminal directly connected to the output terminal of the first tri-statable buffer, a control terminal to turn the second tri-statable buffer on or off, and an output terminal directly connected to the input terminal of the first tri-statable buffer.

1. A passive optical network, comprising:
a broadband light source in a central office to provide broadband incoherent light;
a multiplexer connected to the central office via an optical fiber for filtering the light transmitted from the broadband light source according to wavelengths and multiplexing upstream signals to provide a first plurality of wavelengths;
at least one splitter coupled to the multiplexer for branching a wavelength of the first plurality of wavelengths and combining the upstream optical signals; and
a plurality of wavelength-locked Fabry-Perot laser diodes connected to the at least one splitter to share the branched wavelength that is injected through the splitter to determine an oscillation wavelength of the plurality of wavelength-locked Fabry-Perot laser diodes, the wavelength-locked Fabry-Perot laser diodes capable of performing direct and analog modulation, and a control unit to directly modulate lights of the Fabry-Perot laser diodes and transmitting modulated lights to subscribers using time division multiplexing.
2. The passive optical network of claim 1, wherein the central office modulates the downstream broadband incoherent light to a synchronization signal, and provides the synchronization signal to the subscribers as a reference clock.
3. The passive optical network of claim 2, wherein distances from the at least one splitter to the subscribers are kept similar to minimize guard time to set up connection between the central office and the subscribers.
4. The passive optical network of claim 1, wherein the central office and the multiplexer are connected via a single optical fiber so that bi-directional transmission is enabled.
5. A passive optical network, comprising:
a broadband light source in a central office to provide broadband incoherent light;
a multiplexer connected to the central office via an optical fiber for dividing the light transmitted from the broadband light source according to wavelengths to provide a first plurality of lights and to multiplexing upstream signals;
at least one splitter coupled to the multiplexer for branching a wavelength of the first plurality of lights and combining the upstream optical signals; and
a plurality of wavelength-locked Fabry-Perot laser diodes connected to the at least one splitter to share the branched wavelength that injected through the splitter to determine an oscillation wavelength of the plurality of wavelength-locked Fabry-Perot laser diodes, the wavelength-locked Fabry-Perot laser diodes capable of performing direct and analog modulation, and a control unit to directly modulate the Fabry-Perot laser diodes using subcarrier modulation and transmitting the modulated lights to subscribers.
6. The passive optical network of claim 5, wherein the subcarrier modulation is one of a Frequency Shift Keying (FSK), Phase Shift Keying (PSK) and Quadrature Amplifier Modulation (QAM).
7. The passive optical network of claim 5, wherein, when one or more of the subscribers do not transmit data, the light providing means lowers power of the light and thus reducing optical Beat Interference Noise (OBI), so that a number of subscribers are statically increased.
8. The passive optical network of claim 5, wherein the central office and the multiplexer are connected via a single optical fiber so that bi-directional transmission is enabled.
9. A method, comprising:
supplying broadband light;
filtering the broadband light transmitted according to wavelengths to provide a first plurality of wavelengths;
injecting, through the splitter, a filtered wavelength of the first plurality of wavelengths into a plurality of wavelength-locked Fabry-Perot laser diodes, to provide output lights, so that the injected wavelength that is shared between the plurality of wavelength-locked Fabry-Perot laser diodes through the splitter determines an oscillation wavelength of the plurality of wavelength-locked Fabry-Perot laser diodes; and
modulating the output lights of the Fabry-Perot laser diodes.
10. The method of claim 9, further comprising
multiplexing upstream signals; and
combining the upstream signals.
11. The method of claim 9, further comprising
transmitting the modulated output lights by time division multiplexing.
12. The method of claim 9, wherein the output lights are modulated using subcarrier modulation.
13. The method of claim 9, further comprising
modulating the broadband light to provide a synchronization signal as a reference clock.
14. An apparatus, comprising:
a broadband light source to provide broadband light;
a multiplexer for filtering broadband light according to wavelengths to provide a first plurality of wavelengths;
a splitter coupled to the multiplexer to branch a wavelength of the first plurality of wavelengths; and
a plurality of wavelength-locked Fabry-Perot laser diodes connected to the splitter to share the branched wavelength that is injected through the splitter to determine an oscillation wavelength of the plurality of wavelength-locked Fabry-Perot laser diodes.
15. The apparatus of claim 14, wherein the broadband light is modulated.
16. The apparatus of claim 14, further comprising
a control unit to modulate lights of the Fabry-Perot laser diodes.
17. The apparatus of claim 16, wherein the modulated output lights are transmitted from the Fabry-Perot laser diodes by time division multiplexing.
18. The method of claim 16, wherein the modulated output lights are transmitted from the Fabry-Perot laser diodes by subcarrier modulation.
19. A system, comprising:
means for supplying broadband light;
means for filtering the broadband light according to wavelengths to provide a first plurality of wavelengths;
means for injecting, through the splitter, a filtered wavelength of the first plurality of wavelengths into a plurality of wavelength-locked Fabry-Perot laser diodes to provide output lights, so that the injected wavelength that is shared between the plurality of wavelength-locked Fabry-Perot laser diodes through the splitter determines an oscillation wavelength of the output lights; and
means for modulating the output lights of the Fabry-Perot laser diodes.
20. The system of claim 19, further comprising
means for modulating the broadband light.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A sodium ion absorption andor inducible nitric oxide synthase (iNOS) inhibiting camphanylidene or phenyl alkyl inositol polyphosphate compound, or a stereoisomer, racemate, prodrug or a pharmaceutically acceptable salt thereof.
2. A camphanylidene inositol polyphosphate compound selected from the group consisting of 2,3-camphanylidene-myo-inositol 1,4,5,6-tetrakisphosphate, 1,2-camphanylidene-myo-inositol 3,4,5,6-tetrakisphosphate, and the stereoisomers, racemates, prodrugs, esters and pharmaceutically acceptable salts thereof.
3. A compound of claim 2, which is an ester selected from the group consisting of acetoxymethylesters (AM-esters), propionoxymethylesters (PM-esters) or pivaloyloxymethyl esters.
4. A compound of claim 3 selected from the group consisting of 2,3-camphanylidene-myo-inositol 1,4,5,6-tetrakisphosphate octakis (propionoxymethyl) ester, and 1,2-camphanylidene-myo-inositol 3,4,5,6-tetrakisphosphate octakis (propionoxymethyl) ester, and the stereoisomers, racemates, prodrugs, and pharmaceutically acceptable salts thereof.
5. A method for inhibiting sodium ion absorption by epithelial cells, comprising treating the cells with an effective amount of a sodium uptake inhibiting camphanylidene andor phenyl alkyl inositol polyphosphate compound.
6. A method for inhibiting sodium ion absorption by epithelial cells in a human or animal patient in need of such treatment, comprising administering to the patient a therapeutically effective amount of a sodium uptake inhibiting camphanylidene andor phenyl alkyl inositol polyphosphate compound.
7. A method of claim 6, wherein the sodium uptake inhibiting camphanylidene andor phenyl alkyl inositol polyphosphate compound is a sodium uptake inhibiting inositol polyphosphate compound.
8. A method of claim 6, wherein the camphanylidene inositol polyphosphate compound is selected from the group consisting of 2,3-camphanylidene-myo-inositol 1,4,5,6-tetrakisphosphate, 1,2-camphanylidene-myo-inositol 3,4,5,6-tetrakisphosphate, and the stereoisomers, racemates, prodrugs, esters and a pharmaceutically acceptable salts thereof.
9. A method of claim 8, which is an ester selected from the group consisting of acetoxymethylesters (AM-esters), propionoxymethylesters (PM-esters) or pivaloyloxymethyl esters.
10. A method of claim 9 selected from the group consisting of 2,3-camphanylidene-myo-inositol 1,4,5,6-tetrakisphosphate octakis (propionoxymethyl) ester, and 1,2-camphanylidene-myo-inositol 3,4,5,6-tetrakisphosphate octakis (propionoxymethyl) ester, and the stereoisomers, racemates, prodrugs, and pharmaceutically acceptable salts thereof.