Author: claimsbot

1-14. (canceled)
15. A collapsible bar comprising first and second support members, a surface element, and means for releasably latching the surface element to the first and second support members.
16. A collapsible bar as claimed in claim 15, wherein the releasable latching means includes an elongate channel on each support member and two skirt-portions on the surface element, the skirt-portions being receivable in the channels as a close fit.
17. A collapsible bar as claimed in claim 16, wherein each channel is open-ended and wherein the releasable latching means also includes a latch element which can slidably receive the open-end edge of the channel.
18. A collapsible bar as claimed in claim 17, wherein the latch element is formed on a free-edge of the skirt-portion.
19. A collapsible bar as claimed in claim 16, wherein each support member is in the form of a frame having, in use, front and back uprights and a plurality of horizontal cross-members interconnecting the front and back uprights.
20. A collapsible bar as claimed in claim 15, wherein the surface element is selectable depending on requirement from a range of surface elements having different functions.
21. A collapsible bar as claimed in claim 15, wherein the surface element is selectively positionable on the first and second support members, is repositionable on the first and second support members and is interchangeable with another surface element.
22. A collapsible bar as claimed in claim 15, further comprising a bar-top element, which is supportable by the first and second support members, and means for releasably retaining the bar-top element on the first and second support members.
23. A collapsible bar as claimed in claim 22, wherein the bar-top element is hingably jointed to enable folding.
24. A collapsible bar as claimed in claim 15, further comprising a screen wall for screening the front and sides of the in use bar from patrons.
25. A collapsible bar as claimed in claim 24, wherein the screen wall is hingably jointed to enable folding.
26. A collapsible bar as claimed in claim 24, wherein the screen wall is freestanding.
27. A collapsible bar as claimed in claim 24, wherein the screen wall can be releasably latched to the support members via the releasable latching means.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electrical connector system comprising:
a first connector comprising:
a first connector mating interface;
a plurality of first electrical contacts disposed along the first connector mating interface; and
one or more first magnetic structures wherein a portion of a first magnetic structure is positioned behind each of the first electrical contacts;
a second connector comprising:
a second connector housing having a second connector mating interface;
a plurality of second electrical contacts disposed along the second connector mating interface; and
a compliant substrate; and
a plurality of second magnetic structures affixed to the compliant substrate wherein a portion of a second magnetic structure is positioned behind each of the second electrical contacts; and
a source of magnetic flux providing a magnetic attraction between the one or more first magnetic structures and the second magnetic structures; and
wherein the magnetic attraction moves the second magnetic structures relative to the second connector housing as the first connector mating interface approaches the second connector mating interface.
2. The electrical connector system of claim 1 wherein the second magnetic structures are affixed within cavities of the second connector housing.
3. The electrical connector system of claim 1 wherein the compliant substrate is located between the second electrical contacts and the second magnetic structures.
4. The electrical connector system of claim 3 wherein the second electrical contacts comprise rigid electrical contact structures affixed to the front side of the compliant substrate.
5. The electrical connector system of claim 4 wherein the rigid electrical contact structures comprise magnetic material.
6. The electrical connector system of claim 1 wherein the second electrical contacts comprise conducting surfaces of the second magnetic structures.
7. The electrical connector system of claim 1 further comprising an aperture in the second connector housing and wherein portions of one or more second magnetic structures extend into the aperture.
8. The electrical connector system of claim 1 wherein at least one first magnetic structure comprises
a magnet having a first pole face and a second pole face; and
a first ferromagnetic element comprising magnetic material that is not a magnet wherein the first ferromagnetic element is positioned proximate to the first pole face of the magnet and wherein the first ferromagnetic element directs magnetic flux through a first electrical contact in a direction substantially perpendicular to the first connector mating interface.
9. The electrical connector system of claim 8 wherein the first connector further comprises:
a plurality of third electrical contacts disposed along the first connector mating interface; and
a second ferromagnetic element comprising magnetic material that is not a magnet and wherein the second ferromagnetic element is positioned proximate to the second pole face of the magnet; and
wherein the second ferromagnetic element directs magnetic flux through a third electrical contact in a direction substantially perpendicular to the first connector mating interface; and

the second connector further comprises:
a plurality of fourth electrical contacts disposed along the second connector mating interface; and
wherein at least one of the second magnetic structures comprises ferromagnetic material that is not a magnet wherein the second magnetic structure provides a magnetic flux path between a second electrical contact and a fourth electrical contact.
10. The electrical connector system of claim 1 wherein the magnetic flux passes in the same direction through adjacent second electrical contacts.
11. The electrical connector system of claim 1 wherein at least one of the first magnetic structures comprises a magnet having a first pole face and a second pole face wherein the first pole face is located closer than the second pole face to the first connector mating interface.
12. The electrical connector system of claim 1 comprising two first magnetic structures and two second magnetic structures wherein
one of the first magnetic structures comprises
a first axially magnetized magnet having its magnetic axis oriented perpendicular to the first connector mating interface;

one of the first magnetic structures comprises
magnetic material that is not a magnet located laterally adjacent to the first axially magnetized magnet;

one of the second magnetic structures comprises
a second axially magnetized magnet having its magnetic axis oriented perpendicular to the second connector mating interface; and

one of the second magnetic structures comprises magnetic material that is not a magnet located laterally adjacent to the second axially magnetized magnet;
wherein as the first connector mating interface approaches the second connector mating interface:
the first axially magnetized magnet is attracted to the second magnetic structure comprising magnetic material that is not a magnet;
the first axially magnetized magnet is repelled from the second axially magnetized magnet; and
the second axially magnetized magnet is attracted to the first magnetic structure comprising magnetic material that is not a magnet.
13. The electrical connector system of claim 1 wherein the magnetic flux density through the second electrical contacts is higher than the magnetic flux density through the space between adjacent second electrical contacts.
14. The electrical connector system of claim 1 wherein the connector system provides electrical continuity through a wall of a case for an electronic device.
15. The electrical connector system of claim 1 wherein the plurality of first electrical contacts or the plurality of second electrical contacts at least partially define a portion of a letter or logo.
16. The electrical connector system of claim 1 wherein the one or more second magnetic structures comprise magnetic material that is not a permanent magnet and wherein the smallest distance from a second electrical contact to a second magnetic structure is less than the smallest distance from the second electrical contact to the compliant substrate.
17. The electrical connector system of claim 16 wherein the compliant substrate comprises an aperture and wherein a portion of a second magnetic structure extends through the aperture.
18. The electrical connector system of claim 1 wherein the first magnetic structure comprises
an axially polarized magnet having a first magnetic pole face and a second magnetic pole face wherein the flux path inside the magnet between the first and second magnetic pole faces is substantially parallel to the first connector mating interface; and
a first ferromagnetic pole piece proximate to the first magnetic pole face; and
a second ferromagnetic pole piece proximate to the second magnetic pole face.
19. The electrical connector system of claim 18 characterized by a magnetic flux circuit wherein the magnetic flux circuit comprises a path through the first magnetic pole face, the first ferromagnetic pole piece, a first electrical contact, a second electrical contact, a second magnetic structure, the second ferromagnetic pole piece and the second magnetic pole face.
20. The electrical connector system of claim 18 comprising an electronic substrate wherein a portion of the electronic substrate is positioned between the first magnetic pole face and the first ferromagnetic pole piece.

What is claimed is:

1. Method for manufacturing a silicon wafer (100) from a first silicon wafer (110), comprising a surface layer (402) on an insulating intermediate layer (902) arranged upon a substrate (901), and a second silicon wafer (400) with a surface by bonding the two wafers (110,400) by their respective surfaces, wherein
at least one insulating layer (401) is applied to the surface of at least one silicon wafer (110,400) before bonding, and
the substrate (901) of the first silicon wafer (110) is removed after bonding.
2. Method according to claim 1, wherein the substrate (901) on the first wafer (110) is removed selectively with regard to the insulating intermediate layer (902).
3. Method according to claim 1, wherein the insulating intermediate layer (902) of the first wafer (110) is removed.
4. Method according to claim 1, wherein an oxide layer is created as an insulating layer (401) on the surface of at least one of the two silicon wafers (110, 400) before bonding.
5. Method according to claim 4, wherein the oxide layer is created exclusively on the surface of the first wafer (110), preferably by deposition.
6. Method according to claim 1, wherein at least one of the characteristic parameters, such as for example the resistance or the thickness of the surface layer of the first wafer (110), is changed before bonding.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A physical layer device, comprising:
a mode selector that selects a mode;
a clock that selects a clock frequency from T clock frequencies based on said mode;
a converter module that selects one of N mapping functions based on said mode and that converts an n-bit input to an m-bit output based on said selected one of said N mapping functions;
a scrambler module that scrambles said m-bit output or passes said m-bit output unchanged based on said mode; and
an encoding module that modulates said m-bit output based on said selected clock frequency and one of M modulation modes selected based on said mode;
where T, n, m, N and M are integers greater than one and n is not equal to m.
2. The physical layer device of claim 1 wherein said encoding module modulates said m-bit output based on a first one of said N mapping functions to X level output signals and a second one of said N mapping functions to Y level output signals, where X and Y are integers greater than one and X is different than Y.
3. The physical layer device of claim 2 wherein said X and Y level output signals have positive and negative output levels and wherein said second one of said N mapping functions reduces a number of adjacent symbols in said Y level output signal that have positive levels and a number of adjacent symbols in said Y level output signal that have negative levels as compared to using said first one of said mapping functions with said Y level output signal.
4. The physical layer device of claim 2 wherein said Y level output signals include pulse amplitude modulated (PAM) signals.
5. The physical layer of claim 2 wherein said X level output signals include one bit per symbol and wherein said Y level output signals include two bits per symbol.
6. The physical layer device of claim 1 wherein said encoding module selects one of multi-level 3 (MLT3) modulation, non-return to zero inverted (NRZI) modulation and pulse amplitude modulation (PAM).
7. The physical layer device of claim 1 wherein said physical layer device is connected to copper cable or fiber-optic cable.
8. The physical layer device of claim 1 wherein said physical layer device supports 100BASE-TX, 100BASE-FX, double speed 100BASE-TX and quad speed 100BASE-TX.
9. A method comprising:
selecting a mode;
selecting a clock frequency from T clock frequencies based on said mode;
selecting one of N mapping functions based on said mode;
converting an n-bit input to an m-bit output using said selected one of said N mapping functions;
scrambling said m-bit output or passing said m-bit output unchanged based on said mode; and
modulating said m-bit output based on said selected clock frequency and one of M modulation modes selected based on said mode,
where T, n, m, N and M are integers greater than one and n is not equal to m.
10. The method of claim 9 further comprising modulating said m-bit output based on a first one of said N mapping functions to X level output signals and said m-bit output based on a second one of said N mapping functions to Y level output signals, where X and Y are integers greater than one and X is different than Y.
11. The method of claim 10 wherein said Y level output signals include pulse amplitude modulated (PAM) signals.
12. The method of claim 10 wherein said X level output signals include one bit per symbol and wherein said Y level output signals include two bits per symbol.
13. The method of claim 9 further comprising selecting said mode based on a selected one of a plurality of protocols.
14. The method of claim 9 further comprising selecting between multi-level 3 (MLT3) modulation, non-return to zero inverted (NRZI) modulation and pulse amplitude modulation (PAM).
15. The method of claim 9 further comprising connecting said physical layer device to copper cable or fiber-optic cable.
16. The method of claim 9 wherein said physical layer device supports 100BASE-TX, 100BASE-FX, double speed 100BASE-TX and quad speed 100BASE-TX.
17. A physical layer device, comprising:
mode selecting means for selecting a mode;
clock means for generating a selected clock frequency from T clock frequencies selected based on said mode;
converter means for selecting one of N mapping functions based on said mode and for converting an n-bit input to an m-bit output based on said selected one of said N mapping functions;
scrambling means for scrambling said m-bit output or for passing said m-bit output unchanged based on said mode; and
encoding means for modulating said m-bit output based said selected clock frequency and on one of M modulation modes selected based on said mode,
where T, n, m, N and M are integers greater than one and n is not equal to m.
18. The physical layer device of claim 17 wherein said encoding means selectively modulates said m-bit output based on a first one of said N mapping functions to X level output signals and a second one of said N mapping functions to Y level output signals, where X and Y are integers greater than one and X is different than Y.
19. The physical layer device of claim 18 wherein said X and Y level output signals have positive and negative output levels and wherein said second one of said N mapping functions reduces a number of adjacent symbols in said Y level output signal that have positive levels and a number of adjacent symbols in said Y level output signal that have negative levels as compared to using said first one of said mapping functions with said Y level output signal.
20. The physical layer device of claim 18 wherein said Y level output signals include pulse amplitude modulated (PAM) signals.
21. The physical layer of claim 18 wherein said X level output signals include one bit per symbol and wherein said Y level output signals include two bits per symbol.
22. The physical layer device of claim 17 wherein said encoding means selects one of multi-level 3 (MLT3) modulation, non-return to zero inverted (NRZI) modulation and pulse amplitude modulation (PAM).
23. The physical layer device of claim 17 wherein said physical layer device is connected to copper cable or fiber-optic cable.
24. The physical layer device of claim 17 wherein said physical layer device supports 100BASE-TX, 100BASE-FX, double speed 100BASE-TX and quad speed 100BASE-TX.