1. A lithium secondary battery comprising:
a positive electrode; a negative electrode; and a sulfide solid electrolyte disposed between the positive electrode and the negative electrode, wherein the positive electrode comprises a positive active material particle and a coating film including an oxide comprising lithium (Li) and zirconium (Zr) on a surface of the positive active material particle.
2. The lithium secondary battery of claim 1, wherein
an average secondary particle diameter D50 of the positive active material particle and the coating film is 5 micrometers or less.
3. The lithium secondary battery of claim 1, wherein
the oxide containing lithium (Li) and zirconium (Zr) is a compound of Formula 1:
aLi2O\u2014ZrO2\u2003\u2003Formula 1
wherein 0.1\u2266a\u22662.0.
4. The lithium secondary battery of claim 3, wherein in Formula 1, a is 1.
5. The lithium secondary battery of claim 3, wherein an amount of Li2O\u2014ZrO2 is in a range of about 0.01 to about 2 mole percent, based on a total weight of the positive active material particle and the compound of Formula 1.
6. The lithium secondary battery of claim 5, wherein the amount of Li2O\u2014ZrO2 is in a range of about 0.01 to about 0.95 mole percent, based on the total weight of the positive active material particle and the compound of Formula 1.
7. The lithium secondary battery of claim 1, wherein the positive active material particle is Li1-x-y-zNixCoyAlzO2 wherein 0<x<1, 0<y<1, 0<z<1, and x+y+z<1, Li1-x-y-zNixCoyMnzO2 wherein 0<x<1, 0<y<1, 0<z<1, and x+y+z<1, or a combination thereof.
8. The lithium secondary battery of claim 1, wherein the sulfide solid electrolyte comprises lithium sulfide and phosphorus pentasulfide.
9. The lithium secondary battery of claim 8, wherein a ratio of the lithium sulfide to the phosphorus pentasulfide is in a range of about 50:50 to about 80:20.
10. The lithium secondary battery of claim 1, wherein
the positive active material particle has a D10 particle diameter of about 2.0 micrometers to about 3.5 micrometers, a D50 particle diameter of about 3.0 micrometers to about 5.0 micrometers, and a D90 particle diameter of about 3.5 micrometers to about 5.0 micrometers.
11. The lithium secondary battery of claim 1, wherein
a D10 particle diameter of the positive active material particle is about 2.5 micrometers,
a D50 particle diameter of the positive active material particle is about 3.3 micrometers, and
a D90 particle diameter of the positive active material particle is about 4.5 micrometers.
12. The lithium secondary battery of claim 3, wherein the sulfide solid electrolyte comprises at least one of Li2S and P2S5, and an amount of the compound of Formula 1 is in a range of about 0.1 to about 2.0 mole percent, based on the total amount of the positive active material particle and the compound of Formula 1.
13. The lithium secondary battery of claim 1, wherein the positive active material has a layered rock salt structure.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package comprising:
a first fan-out tier comprising:
a first device die;
a first molding compound extending along sidewalls of the first device die; and
a first through intervia (TIV) extending through the first molding compound;
one or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;
a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;
one or more second fan-out RDLs on an opposing side of the first fan-out tier as the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; and
a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.
2. The package of claim 1, wherein the second fan-out tier further comprises:
a second molding compound extending along sidewalls of the second device die; and
a second TIV extending through the second molding compound.
3. The package of claim 2, wherein the second fan-out tier further comprises a third device die bonded to one or more first fan-out RDLs, wherein the second TIV is disposed between the second and the third device dies.
4. The package of claim 2, wherein the second fan-out tier further comprises a fourth device die, wherein back surfaces of the second device die and the fourth device die are bonded by an adhesive layer.
5. The package of claim 1, further comprising one or more third fan-out RDLs between the one or more first fan-out RDLs and the second fan-out tier, wherein the second device die is bonded to the one or more third fan-out RDLs, and wherein a plurality of connectors bonds the one or more third fan-out RDLs to the one or more second fan-out RDLs.
6. The package of claim 1 further comprising:
one or more third fan-out RDLs over the second fan-out tier, wherein the one or more third fan-out RDLs is electrically connected to the one or more second fan-out RDLs; and
a third fan-out tier disposed over the one or more third fan-out RDLs, the third fan-out tier comprising a fifth device die bonded to the one or more third fan-out RDLs, and wherein the one or more third fan-out RDLs electrically connects the fifth device die to the first device die.
7. The package of claim 1 further comprising one or more heat dissipation features on a surface of the package.
8. A package comprising:
a first device die;
a first fan-out tier bonded to the first device die, the first fan-out tier comprising:
a second device die;
a first molding compound extending along sidewalls of the second device die; and
a first through intervia (TIV) extending through the first molding compound;
a first fan-out RDL bonded to the first fan-out tier; and
a third device die electrically connected to the first fan-out RDL, wherein the first device die is electrically connected to the third device die by a first dedicated signaling path comprising the first TIV.
9. The package of claim 8, wherein the first device die and the second device die are electrically isolated from each other.
10. The package of claim 8, the second device die comprises a through-silicon via (TSV), wherein the TSV electrically connects the first and the second device dies.
11. The package of claim 8, wherein the third device die is disposed in a second fan-out tier, the second fan-out tier further comprising:
a second molding compound extending along sidewalls of the third device die; and
a second TIV extending through the second molding compound, wherein the first dedicated signaling path comprises the second TIV.
12. The package of claim 8, wherein the second device die is electrically connected to the third device die by a second dedicated signaling path, the second dedicated signaling path being electrically isolated from the first dedicated signaling path.
13. The package of claim 8, wherein the first device die is disposed in a second fan-out tier, and wherein the first device die is bonded to a second fan-out RDL disposed between the first and the second fan-out tiers.
14. The package of claim 8, wherein the first dedicated signaling path electrically connects the first device die to an external connector disposed on a surface of the package.
15. A method for forming a package comprising:
forming one or more first fan-out redistribution layers (RDLs) comprising a conductive line;
forming a fan-out tier over the one or more first fan-out RDLs, wherein forming the fan-out tier comprises:
forming a first through intervia (TIV) over the one or more first fan-out RDLs;
bonding a first device die to the one or more first fan-out RDLs;
dispensing a first molding compound around the first device die and the first TIV; and
exposing connectors on the first device die and the first TIV;
forming one or more second fan-out RDLs over the fan-out tier, wherein the first TIV electrically connects the one or more second fan-out RDLs to the one or more first fan-out RDLs;
bonding a second device die to the one or more second fan-out RDLs, wherein the one or more second fan-out RDLs electrically connects the first and the second device dies;
patterning the one or more first fan-out RDLs to expose the conductive line; and
disposing an external connector on the conductive line, wherein the external connector is at least partially disposed in the one or more first fan-out RDLs.
16. The method of claim 15, wherein patterning the one or more first fan-out RDLs to expose the conductive line comprises laser drilling.
17. The method of claim 15, wherein bonding the first device die comprises adhering the first device die to the one or more first fan-out RDLs using an adhesive layer on a backside of the first device die.
18. The method of claim 15, further comprising:
forming a second TIV over the one or more second fan-out RDLs;
dispensing a second molding compound around the second device die and the second TIV;
exposing the second TIV;
forming one or more third fan-out RDLs over the second TIV and the second device die, wherein the second TIV electrically connects the one or more third fan-out RDLs to the one or more second fan-out RDLs; and
bonding a third device die to the one or more third fan-out RDLs, wherein the one or more third fan-out RDLs electrically connects the first and the third device dies.
19. The method of claim 15 wherein forming the first TIV comprises:
disposing a photoresist over the one or more first fan-out RDLs;
patterning an opening in the photoresist;
filling the opening with a conductive material; and
removing the photoresist.
20. The method of claim 19, wherein forming the first TIV further comprises disposing seed layer between the photoresist and the one or more fan-out RDLs, wherein the opening exposes the seed layer, and wherein filling the opening comprises using the seed layer in a uni-directional electroless or electrochemical plating process.