Author: claimsbot

1. A low electromagnetic interference (\u201cEMI\u201d) voltage measurement system comprising:
an input selection device configured to receive a plurality of analog voltage signals and output one of the plurality of analog voltage signals;
a converter circuit coupled to the input selection device, the converter circuit configured to convert at least a first analog voltage signal to a first digital signal and convert a second analog voltage signal to a second digital signal;
a clock circuit configured to output a clock signal to cause the input selection device to output one of the plurality of analog voltage signals;
a counter circuit coupled to the input selection device, the counter circuit configured to receive the clock signal and to provide input selection logic to the input selection device in response to receiving the clock signal;
a fiber optic transmitter coupled to the converter circuit and configured to transmit the first digital signal to a fiber optic receiver and transmit the second digital signal to the fiber optic receiver; and
a receiver circuit configured to receive at least the transmitted first digital signal and receive the transmitted second digital signal, the receiver circuit including a latching device configured to latch the first digital signal and to latch the second digital signal and in response to latching a predetermined threshold amount of digital signals, the receiver circuit transmits the latched digital signals to a computing device;
wherein the clock signal is based on the discharge rate of a first voltage storage device, the clock signal occurring at a frequency that is below a predetermined threshold frequency such that EMI does not alter operation of a device under test adjacent the low EMI voltage measurement system.
2. The low EMI voltage measurement system of claim 1, wherein the receiver circuit includes a counter device and a transceiver, wherein the counter device and the transceiver cooperate to latch one or more transmitted digital signals.
3. The low EMI voltage measurement system of claim 1, wherein the converter circuit includes a second voltage storage device configured to discharge a first analog voltage signal and the converter circuit is further configured to output a digital signal based on at least the first analog voltage signal being greater than a second analog voltage signal.
4. The low EMI voltage measurement system of claim 2, wherein each digital signal corresponds to an analog voltage signal and indicates an analog voltage value.
5. The low EMI voltage measurement system of claim 2, wherein in response to latching a predetermined amount of digital signals a write pulse causes at least one of the receiver circuit to transmit the latched digital signals to a computing device and the counter device to reset.
6. The low EMI voltage measurement system of claim 1, further including a logic circuit coupled to the converter circuit and coupled to the fiber optic transmitter, the logic circuit configured to at least invert the first digital signal and invert the second digital signal.
7. The low EMI voltage measurement system of claim 4, further including a global position system (\u201cGPS\u201d) receiver coupled to the receiver circuit, the GPS receiver configured to provide universal-time-stamping of the received transmitted digital signals such that receipt of analog voltage values corresponding to the digital signals are synchronize.
8. The low EMI voltage measurement system of claim 1, wherein the low EMI voltage measurement system is operable within a temperature range of \u221220\xb0 C. to +60\xb0 C., includes a voltage measurement accuracy of less than 10 mV, and operates based on a direct current (DC) supply voltage ranging from 5 VDC to 12 VDC.
9. The low EMI voltage measurement system of claim 5, wherein the receiver circuit transmits, to the computing device, a digital data stream of a predetermined byte size, the digital data stream including at least a pulse-width byte and a GPS signal byte wherein the pulse-width byte corresponds to a first decimal value and the GPS signal byte corresponds to a second decimal value that is greater than the first decimal value.
10. A method in a low electromagnetic interference (\u201cEMI\u201d) voltage measurement system comprising:
receiving, by an input selection device, a plurality of analog voltage signals and outputting one of the plurality of analog voltage signals;
converting, by a converter circuit, at least a first analog voltage signal to a first digital signal and a second analog voltage signal to a second digital signal;
providing, by a clock circuit, a clock signal to a counter circuit configured to output input selection logic wherein the clock signal is based on the discharge rate of a first voltage storage device, the clock signal occurring at a frequency that is below a predetermined threshold frequency such that EMI does not alter operation of a device under test adjacent the low EMI voltage measurement system;
providing, by a counter circuit, input selection logic to the input selection device in response to the counter circuit receiving the clock signal wherein the input selection logic causes the input selection device to output one of the plurality of analog voltage signals;
transmitting, by a fiber optic transmitter, the first digital signal to a fiber optic receiver and the second digital signal to the fiber optic receiver;
receiving, by a receiver circuit, at least the transmitted first digital signal and the transmitted second signal wherein the receiver circuit includes a latching device configured to latch the first digital signal and to latch the second digital signal; and
transmitting, by the receiver circuit, at least the latched first digital signal and the latched second digital signal in response to the latching device latching a predetermined threshold amount of digital signals wherein the transmitted latched digital signals are received by a computing device.
11. The method of claim 10, wherein each digital signal corresponds to an analog voltage signal and indicates an analog voltage value.
12. The method of claim 11, wherein the computing device includes recording software and at least one memory module, and the method further includes, recording, by the recording software, one or more digital signals corresponding to one or more analog voltage signals, and in response to recording, storing, by the memory module, the one or more digital signals.
13. The method of claim 11, further including, providing, by a global positioning system (\u201cGPS\u201d) receiver, a universal-time-stamp of the received transmitted digital signals such that receipt, by the low EMI voltage measurement system, of analog voltage values corresponding to the digital signals are synchronized.
14. The method of claim 10, wherein the low EMI voltage measurement system is operable within a temperature range of \u221220\xb0 C. to +60\xb0 C., includes a voltage measurement accuracy of less than 1 OmV, and operates based on a direct current (DC) supply voltage ranging from 5 VDC to 12 VDC.
15. The method of claim 10, wherein the converter circuit includes a second voltage storage device and the method further includes, discharging, by the second voltage storage device, a first analog voltage signal such that the converter circuit outputs a digital signal based on at least the first analog voltage signal being greater than a second analog voltage signal.
16. A low electromagnetic interference (\u201cEMI\u201d) voltage measurement system comprising:
an input selection device configured to receive a plurality of analog voltage signals and output one of the plurality of analog voltage signals;
a transmitter module coupled to the input selection device, the transmitter module configured to convert an analog voltage signal to a digital signal and transmit the digital signal;
a receiver module coupled to the transmitter module and configured to receive the digital signal, the receiver module including a latching device configured to latch the digital signal and in response to latching a predetermined threshold amount of digital signals, the receiver module transmits the latched digital signals to a computing device; and
a clock circuit coupled to the input selection device and configured to output a clock signal to cause the input selection device to output one of the plurality of analog voltage signals, wherein the clock signal occurs at a frequency that is below a predetermined threshold frequency such that EMI does not alter operation of a device under test adjacent the low EMI voltage measurement system.
17. The low EMI voltage measurement system of claim 16, further including a delay module configured to delay the clock signal such that the input selection device receives the clock signal at a first time period and the transmitter module receives the clock signal at a second time period.
18. The low EMI voltage measurement system of claim 17, wherein the clock signal is based on the discharge rate of a voltage storage device and wherein the clock circuit is a dithered clock circuit such that the periodicity of the clock signal is dithered.
19. The low EMI voltage measurement system of claim 18, further including a counter circuit coupled to the input selection device, the counter circuit providing input selection logic to the input selection device in response to receiving the clock signal.
20. The low EMI voltage measurement system of claim 16, wherein the receiver module includes a counter device and a transceiver, wherein the counter device and the transceiver cooperate to latch one or more digital signals.
21. The low EMI voltage measurement system of claim 20, further including a global positioning system (\u201cGPS\u201d) receiver coupled to the receiver module, the GPS receiver providing a universal-time-stamp of the one or more digital signals wherein the one or more digital signals correspond to an analog voltage signal and indicates an analog voltage value.
22. A low electromagnetic interference (EMI) voltage measurement system comprising:
an input selection device configured to receive a plurality of analog voltage signals and output one of the plurality of analog voltage signals;
a converter circuit coupled to the input selection device, the converter circuit configured to convert at least a first analog voltage signal to a first digital signal, convert a second analog voltage signal to a second digital signal, and output a clock signal;
a counter circuit coupled to the input selection device, the counter circuit configured to receive the clock signal and to provide input selection logic to the input selection device in response to receiving the clock signal;
a logic circuit coupled to the converter circuit, the logic circuit configured to at least invert the first digital signal and invert the second digital signal;
a fiber optic transmitter coupled to the logic circuit and configured to transmit the first digital signal to a fiber optic receiver and transmit the second digital signal to the fiber optic receiver; and
a receiver circuit configured to receive at least the transmitted first digital signal and receive the transmitted second digital signal, the receiver circuit including a latching device configured to latch the first digital signal and to latch the second digital signal and in response to latching a predetermined amount of digital signals, the receiver circuit transmits the latched digital signals to a computing device;
wherein the clock signal is based on the discharge rate of a voltage storage device, the clock signal occurring at a frequency that is below a predetermined threshold frequency such that EMI does not alter operation of a device under test adjacent the low EMI voltage measurement system.
23. A method of configuring and operating a low electromagnetic interference (\u201cEMI\u201d) voltage measurement testing system in proximity with a device under test comprising:
providing a voltage testing system comprising a clock circuit;
providing, by the clock circuit, a clock signal to a counter circuit configured to output input selection logic wherein the clock signal is based on the discharge rate of a first voltage storage device, the clock signal occurring at a frequency that is below a threshold frequency;
providing an input selection device configured to receive a plurality of analog voltage signals and output one of the plurality of analog voltage signals;
providing a converter circuit coupled to the input selection device, the converter circuit configured to convert at least a first analog voltage signal to a first digital signal and convert a second analog voltage signal to a second digital signal;
providing a device under test having a receiver configured to operate in response to receiving a radio frequency (\u201cRF\u201d) signal;
positioning the voltage testing system in close proximity to the device under test;
determining, by an assessment module, a plurality of device under test electromagnetic interference (\u201cEMI\u201d) vulnerability characteristics comprising one or more operating signal frequencies of the device under test;
configuring the voltage testing system comprising configuring the clock circuit to operate at a frequency other than the one or more operating signal frequencies of the device under test
receiving, by the input selection device, a plurality of analog voltage signals and outputting one of the plurality of analog voltage signals;
converting, by the converter circuit, at least a first analog voltage signal to a first digital signal and a second analog voltage signal to a second digital signal;
providing, by a counter circuit, input selection logic to the input selection device in response to the counter circuit receiving the clock signal wherein the input selection logic causes the input selection device to output one of the plurality of analog voltage signals;
providing a fiber optic interface cable coupled to an optical output signal interface section of a transmitter of the voltage testing system and an optical input signal interface section of a receiver of the voltage testing system;
transmitting, by the fiber optic interface cable, the first digital signal to the optical input signal interface section of the receiver and the second digital signal to the optical input signal interface section of the receiver;
receiving, by the optical input signal interface section of the receiver, at least the transmitted first digital signal and the transmitted second signal wherein the receiver includes a latching device configured to latch the first digital signal and to latch the second digital signal; and
transmitting, by the receiver, at least the latched first digital signal and the latched second digital signal in response to the latching device latching a predetermined threshold amount of digital signals wherein the transmitted latched digital signals are received by a computing device; and
generating a plurality of outputs comprising one or more digital data bytes.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor light emitting device comprising:
a semiconductor lamination including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer;
a rhodium (Rh) layer formed on one surface of the semiconductor lamination;
a light reflecting layer containing Ag, formed on the Rh layer and having an area smaller than the Rh layer; and
a cap layer covering the light reflecting layer to encapsulate the light reflecting layer together with the Rh layer.
2. The semiconductor light emitting device according to claim 1, wherein the light reflecting layer has a larger in-plan area at a side near the Rh layer than at a side near the cap layer.
3. The semiconductor light emitting device according to claim 1, further comprising:
a support substrate;
a eutectic layer coupling the cap layer with the support substrate; and
a wiring electrode layer formed on another surface of the semiconductor lamination.
4. The semiconductor light emitting device according to claim 1, wherein the Rh layer has a thickness in a range of 0.1 nm to 1 nm.
5. A method for manufacturing a semiconductor light emitting device comprising steps of:
(a) preparing a growth substrate;
(b) growing a semiconductor lamination on the growth substrate, including a first semiconductor layer of a first conductivity type, an active layer on the first semiconductor layer, and a second semiconductor layer of a second conductivity type on the active layer;
(c) forming a rhodium (Rh) layer on one surface of the semiconductor lamination;
(d) forming a light reflecting layer containing Ag on the Rh layer;
(e) etching the light reflecting layer to pattern the light reflecting layer to be defined only within an area of the Rh layer; and to have an area smaller than the area of the Rh layer; and
(f) forming a cap layer covering the light reflecting layer to encapsulate the light reflecting layer together with the Rh layer.
6. The method for manufacturing a semiconductor light emitting device according to claim 5, wherein the step (e) produces the light reflecting layer having in-plan area wider at a side near the Rh layer than at a side near the cap layer.
7. The method for manufacturing a semiconductor light emitting device according to claim 5, further comprising steps of:
(g) forming a Au layer on the cap layer;
(h) preparing a support substrate having a eutectic layer formed on one principal surface; and
(i) abutting the Au layer with the eutectic layer, and carrying out eutectic reaction.
8. The method for manufacturing a semiconductor light emitting device according to claim 7, further comprising:
(j) removing the growth substrate; and
(k) forming a wiring electrode on a surface of the semiconductor lamination exposed in the step (j).
9. The method for manufacturing a semiconductor light emitting device according to claim 5, wherein the step (c) forms the Rh layer with a thickness in a range of 0.1 nm to 1 nm.

1. An olefin polymer having a melt index of less than or equal to about 50 g10 min, a ratio of MwMn in a range from about 4 to about 20, a density in a range from about 0.90 gcm3 to about 0.945 gcm3, and a substantially constant short chain branch distribution (SCBD).
2. The polymer of claim 1, wherein the olefin polymer has:
a Mn in a range from about 8,000 to about 30,000 gmol; and
a ratio of MwMn in a range from about 4 to about 10.
3. The polymer of claim 1, wherein the olefin polymer has:
a density in a range from about 0.91 to about 0.94 gcm3;
a ratio of HLMIMI in a range from about 10 to about 100;
a Mw in a range from about 50,000 to about 300,000 gmol; and
a ratio of MzMw in a range from about 2 to about 5.
4. The polymer of claim 1, wherein the olefin polymer is an ethylene1-butene copolymer, an ethylene1-hexene copolymer, or an ethylene1-octene copolymer.
5. An article comprising the olefin polymer of claim 4.
6. The polymer of claim 1, wherein the olefin polymer has:
a melt index in a range from about 0.1 to about 10 g10 min;
a ratio of MwMn in a range from about 4.1 to about 8;
a density in a range from about 0.915 gcm3 to about 0.945 gcm3; and
a substantially constant short chain branch distribution (SCBD).
7. The polymer of claim 6, wherein the olefin polymer is an ethylene1-butene copolymer, an ethylene1-hexene copolymer, or an ethylene1-octene copolymer.
8. The polymer of claim 7, wherein the olefin polymer has:
less than about 0.008 long chain branches per 1000 total carbon atoms; and
a bimodal molecular weight distribution.
9. The polymer of claim 7, wherein the olefin polymer has:
a ratio of HLMIMI in a range from about 10 to about 250; and
a ratio of MzMw in a range from about 2 to about 4.
10. An article comprising the olefin polymer of claim 7.
11. A polymerization process, the process comprising:
contacting a catalyst composition with an olefin monomer and an optional olefin comonomer in a polymerization reactor system under polymerization conditions to produce an olefin polymer, wherein the catalyst composition comprises catalyst component I, catalyst component II, an activator, and an optional co-catalyst, wherein:
catalyst component I comprises a boron bridged metallocene compound with a cyclopentadienyl group and an indenyl group; and
catalyst component II comprises a single atom bridged metallocene compound with a fluorenyl group.
12. The process of claim 11, wherein:
the catalyst composition comprises an organoaluminum co-catalyst; and
the activator comprises a fluorided solid oxide andor a sulfated solid oxide.
13. The process of claim 11, wherein the activator comprises an aluminoxane compound, an organoboron or organoborate compound, an ionizing ionic compound, or any combination thereof.
14. The process of claim 11, wherein:
the polymerization reactor system comprises a slurry reactor, a gas-phase reactor, a solution reactor, or a combination thereof; and
the olefin monomer comprises ethylene, and the olefin comonomer comprises 1-butene, 1-hexene, 1-octene, or a mixture thereof.
15. The process of claim 11, wherein the olefin polymer is an ethylenea-olefin copolymer characterized by a substantially constant short chain branch distribution.
16. A catalyst composition comprising catalyst component I, catalyst component II, an activator, and an optional co-catalyst, wherein:
catalyst component I comprises a boron bridged metallocene compound having formula (A):
and
catalyst component II comprises a single atom bridged metallocene compound having formula (B):
wherein:
M and M3 independently are Ti, Zr, or Hf;
each X independently is a monoanionic ligand;
Cp is a cyclopentadienyl group, optionally substituted;
Ind is an indenyl group, optionally substituted;
CpC is a cyclopentadienyl group or an indenyl group, optionally substituted;
RX and RY independently are H, a halide, a C1 to C36 hydrocarbyl group, a C1 to C36 halogenated hydrocarbyl group, a C1 to C36 hydrocarboxy group, or a C1 to C36 hydrocarbylsilyl group;
each R independently is H, a C1 to C36 hydrocarbyl group, or a C1 to C36 hydrocarbylsilyl group; and
each R3 independently is H or a C1 to C18 hydrocarbyl group.
17. The composition of claim 16, wherein the activator comprises an aluminoxane compound, an organoboron or organoborate compound, an ionizing ionic compound, or any combination thereof.
18. The composition of claim 16, wherein the catalyst composition comprises a co-catalyst, and wherein the activator comprises an activator-support, the activator-support comprising a solid oxide treated with an electron-withdrawing anion.
19. The composition of claim 16, wherein a weight ratio of catalyst component Ito catalyst component II is in a range of from about 1:10 to about 10:1.
20. The composition of claim 16, wherein:
M and M3 independently are Zr or Hf;
each X independently is a halide or a C1 to C18 hydrocarbyl group;
at least one of Cp and Ind has an alkenyl substituent;
CpC is a cyclopentadienyl group, optionally substituted;
RX and RY independently are a C1 to C8 hydrocarbyl group;
E3 is C or Si;
each R independently is a C1 to C1e hydrocarbyl group; and
each R3 independently is a C1 to C12 hydrocarbyl group.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A dried fibrillated mixture of lyocell fibers and cellulose pulp fibers having a Canadian Standard Freeness of 250 mL CSF or less, wherein the pulp fibers in the mixture is in the range of 10% to 75% of the total weight of the fibers in the mixture and the mixture has a water content from 0% to 30% of the weight of the fibers and water.
2. The mixture of claim 1 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
3. The mixture of claim 1 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.
4. The mixture of claim 1 wherein the pulp fibers in the mixture is in the range of 20% to 70% of the total weight of the fibers in the mixture.
5. The mixture of claim 4 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
6. The mixture of claim 4 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.
7. The mixture of claim 1 wherein the mixture has a water content from 0% to 10% of the weight of the fibers and water.
8. The mixture of claim 7 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
9. The mixture of claim 7 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.
10. A method of providing a dried fibrillated mixture of lyocell fibers and cellulose pulp fibers comprising
fibrillating a mixture of lyocell fibers and cellulose pulp fibers in water to a Canadian Standard Freeness of 250 mL CSF or less, wherein in the pulp fibers in the mixture is in the range of 10% to 75% of the total weight of the fibers in the fiber mixture,
drying the fiber mixture and water until the water content of the mixture is 0% to 30% of the weight of the fibers and water, and the Canadian Standard Freeness is 250 mL CSF or less.
11. The method of claim 10 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
12. The method of claim 10 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.
13. The method of claim 10 wherein the pulp fibers in the mixture is in the range of 20% to 70% of the total weight of the fibers in the fiber mixture.
14. The method of claim 13 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
15. The method of claim 13 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.
16. The method of claim 10 wherein the water content of the mixture is 0% to 10% of the weight of the fibers and water.
17. The method of claim 16 wherein the pulp has a DP of 200 to 1000 as measured by ASTM Test D 1975-96.
18. The method of claim 16 wherein the pulp has a DP of greater than 1000 as measured by ASTM Test D 1975-96.