Author: claimsbot

1. A coreless transformer, comprising first and second windings, said first winding being disposed in a first plane, said second winding being disposed in a second plane proximate and parallel to said first plane, wherein said transformer is adapted to be operated by a high-frequency carrier signal modulated by a low-frequency non-zero switching signal, and wherein said transformer is adapted to be operated only at a frequency that is less than a resonant frequency of said transformer.
2. The transformer as claimed in claim 1, wherein said carrier signal is at an optimum frequency, said optimum frequency being a frequency at which an input impedance of said transformer is a maximum.
3. The transformer as claimed in claim 1, wherein said high frequency carrier signal is in a range of from 300 kHz to 20 MHz and said low frequency non-zero switching signal is in a range of from above DC to 300 kHz.
4. A coreless transformer comprising first and second windings, said first winding being disposed in a first plane, said second winding being disposed in a second plane proximate and parallel to said first winding plane, further comprising means for adjusting a resonant frequency of the transformer, wherein said transformer is adapted to be operated only at a frequency that is less than said resonant frequency of said transformer.
5. The transformer as claimed in claim 4, wherein said adjusting means comprises a capacitance connected directly across the second winding.
6. A method of operating a coreless planar transformer, wherein said transformer is operated at an optimum frequency which is at or near the frequency at which the impedance of a transformer equivalent circuit is at its maximum and which is less than the resonant frequency of the transformer.
7. A method as claimed in claim 6 wherein the transformer is operated at a frequency of between 100 kHz and 20 Mhz.
8. A method as claimed in claim 6 wherein said transformer is operated by a high-frequency carrier signal modulated by a low frequency non-zero switching signal, said carrier signal being at said optimum frequency.
9. A method as claimed in claim 8 wherein said switching signal is at a frequency of less than 300 kHz.
10. A method of driving a gate of a power MOSFET or IGBT device comprising isolating said gate from a power supply by means of a coreless planar transformer and driving said gate at an optimum frequency which is at or near the frequency at which the impedance of a transformer equivalent circuit is at its maximum and which is less than the resonant frequency of the transformer.
11. A method as claimed in claim 10 wherein said gate is driven at a frequency in the range of from about 100 kHz to 20 MHz.
12. A method as claimed in claim 10 wherein a low frequency non-zero switching signal is used to modulate a high-frequency carrier signal input to said transformer, and wherein said carrier signal is demodulated after said transformer to drive said gate at said low switching frequency, said carrier signal being at said optimum frequency.
13. A method as claimed in claim 12 wherein said switching signal is at a frequency of less than 300 kHz.
14. A coreless transformer comprising first and second windings, said first winding being disposed in a first plane, said second winding being disposed in a second plane proximate and parallel to said first plane, said coreless transformer further comprising a capacitance across said second winding to resonate with said coreless transformer in order to maximize an input impedance of the coreless transformer, wherein an operating frequency of the coreless transformer is less than a resonant frequency of the transformer.
15. The coreless transformer of claim 14, wherein said operating frequency is between 300 kHz and 20 MHz.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A seat belt spooling device comprising:
a frame including a pair of sidewalls;
a reel disposed between the pair of sidewalls, for spooling a seat belt;
a resilient member for urging the reel in the spooling direction;
a pretensioner for driving the reel to rotate in the spooling direction in an emergency; and
a locking structure for locking the reel in the emergency,
wherein the pretensioner comprises:
a driven shaft connected to the reel;
balls disposed along one of the sidewalls and around the periphery of the driven shaft;
a gas generator for applying pressure of gas to the balls so as to move around the periphery of the driven shaft; and
a ball-receiving member for receiving the balls which move into the ball-receiving member,

wherein the ball-receiving member extends from said one of the sidewalls to the other one of the sidewalls, and an opening is formed toward an end in the extending direction of the ball-receiving member, the opening opposing said other one of the sidewalls.
2. A seat belt spooling device according to claim 1, further comprising a guide surface integrally formed with the ball-receiving member for guiding the balls which move into the ball-receiving member.
3. A seat belt spooling device according to claim 1, wherein a case disposed around the periphery of the driven shaft, for supporting the balls, is formed integrally with the ball-receiving member.
4. A seat belt spooling device according to claim 3, wherein the case and the ball-receiving member are formed by casting.
5. A seat belt spooling device comprising:
a pretensioner having a plurality of balls;
a ball receiving member positioned to receive the balls following operation of the pretensioner;
wherein the ball receiving member includes a passage for retaining the balls and an inclined surface for guiding the balls into the passage;
wherein the inclined surface is integrally attached to a wall of the passage.
6. The device of claim 5, wherein the passage includes a first opening at a first end of the passage and a second opening at a second end of the passage.
7. The device of claim 6, wherein second opening is blocked by a frame supporting a drive shaft for a spool.

What is claimed is:

1. A semiconductor memory device, comprising:
a memory cell array;
a decoder unit selecting a word line of the memory cell array;
a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line;
a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location;
a timing control unit determining timing of activation and deactivation of an internal control signal, wherein the timing control unit determines the timing of activation of the internal control signal based on a first signal passing the first dummy bit line through a corresponding dummy cell of the first dummy cell array, and determines the timing of deactivation of the internal control signal based on a second signal passing the second dummy bit line through a corresponding dummy cell of the second dummy cell array.
2. The semiconductor memory device of claim 1 wherein the first dummy cell array is disposed at a location nearest to the decoder unit, and the second dummy cell array is disposed at a location farthest from the decoder unit.
3. The semiconductor memory device of claim 2 wherein the timing control unit is provided to determine activation timing of a data latch signal, inputted to a corresponding output latch portion of an IO latch circuit, based on an output signal of a corresponding dummy cell of the first dummy cell array.
4. The semiconductor memory device of claim 2 wherein the timing control unit is provided to determine deactivation timing of a data latch signal, inputted to a corresponding output latch portion of an IO latch circuit, based on an output signal of a corresponding dummy cell of the second dummy cell array.
5. The semiconductor memory device of claim 1 wherein the semiconductor memory device is an SRAM having no sense amplifier.
6. The semiconductor memory device of claim 1 wherein the first dummy cell array is disposed at a location nearest to the decoder unit, and the second dummy cell array is disposed nearly at a central location of the memory cell array.
7. The semiconductor memory device of claim 6 wherein the timing control unit is provided to determine activation timing of a data latch signal, inputted to a corresponding output latch portion of an IO latch circuit, based on an output signal of a corresponding dummy cell of the first dummy cell array.
8. The semiconductor memory device of claim 6 wherein the timing control unit is provided to determine deactivation timing of a data latch signal, inputted to a corresponding output latch portion of an IO latch circuit, based on an output signal of a corresponding dummy cell of the second dummy cell array.
9. The semiconductor memory device of claim 2 further comprising an odd number of inverters connected in series on the first dummy bit line to which the first dummy cell array is connected, and an even number of inverters connected in series on the second dummy bit line to which the second dummy cell array is connected.
10. The semiconductor memory device of claim 6 further comprising an odd number of inverters connected in series on the first dummy bit line to which the first dummy cell array is connected, and an even number of inverters connected in series on the second dummy bit line to which the second dummy cell array is connected.
11. The semiconductor memory device of claim 1 wherein the internal control signal is supplied to an IO latch circuit, and the timing control unit determines activation and deactivation timing of a data latch signal which is inputted to the IO latch circuit.
12. The semiconductor memory device of claim 1 wherein the internal control signal is supplied to a sense amplifier, and the timing control unit determines activation and deactivation timing of a sense amplifier activation signal which is inputted to the sense amplifier.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of mitigating the impact of radiation induced soft errors in a data processor incorporating integrated circuits, the method comprising the steps of:
determining the location of said data processor;
determining a set of radiation sources and intensities at said location;
estimating the soft error rate of said data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value; and
modifying said data processor in response to said estimate value at times said estimate value exceeds a predetermined value.
2. A method according to claim 1, wherein the modifying step includes the step of modifying hardware of the data processor to change the sensitivity of the data processor to the induced soft errors.
3. A method according to claim 1, wherein the modifying step includes the step of modifying software of the data processor to change the sensitivity of the data processor to the induced soft errors.
4. The method of claim 1, wherein said step of determining a set of radiation sources and intensities includes the step of assessing radiation sources including background sources comprising neutrons, protons and pions.
5. The method of claim 4, wherein said radiation sources further include background sources of electrons, nuons and gamma radiation.
6. The method of claim 4, wherein the step of assessing radiation sources includes assessing the susceptibility of soft error rate due to radiation sources such as solar and cosmic radiation.
7. The method of claim 1, wherein said step of estimating the soft error rate includes the step of estimating the soft error rate as a function of integrated circuit technology, dopant profiles and critical dimensions.
8. The method of claim 1, wherein said step of efficient SER estimation, includes the following steps:
(1) table look-ups of a database of probability functions of charge collection; these functions are pre-calculated by Monte Carlo simulations of large samples of particle tracks generated by alpha particles, and secondary particles produced from high-energy cosmic ray particles;
(2) table look-ups of a database of measuredcalculated total cross sections of proton-, neutron-, and pion-nucleus reactions;
(3) table look-ups of a database of measuredcalculated cosmic ray particle fluxes; the database also includes model parameters, which allow one to compute, in real time, the local fluctuations of cosmic ray particle fluxes as functions of particle energy, location of the processor, time of the year and other atmospheric parameters that impact fluctuations of cosmic ray particle fluxes.
9. The method of claim 8, wherein said step of estimating is performed by a general purpose computer, running at 500 MHz, in less than one minute.
10. The method of claim 1, wherein said step of modifying includes at least one of the steps of:
changing the voltage VDD to at least some circuitry in said integrated circuits;
changing the amount of redundancy of selected bits or bytes stored in memory in the integrated circuits;
adding or removing error correction software; and
adding or removing redundant processors.
11. The method of claim 1, wherein the modifying step is done automatically by software to modify the performance of the data processor to be less sensitive to soft errors.
12. The method of claim 1, wherein the modifying step is done manually by the process user to modify the performance of the data processor to be less sensitive to soft errors.
13. A system for mitigating the impact of radiation induced soft errors in a data processor incorporating integrated circuits, the system comprising:
means for storing the location of said data processor;
means for storing a set of radiation sources and intensities at said location;
means for estimating the soft error rate of said data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value; and
means for modifying said data processor in response to said estimate value at times said estimate value exceeds a predetermined value.
14. A system according to claim 13, wherein the means for storing a set of radiation sources and intensities includes means for assessing radiation sources including background sources comprising neutrons, protons and pions.
15. A system according to claim 13, wherein the means for estimating the soft error rate includes means for estimating the soft error rate as a function of integrated circuit technology, dopant profiles and critical dimensions.
16. A system according to claim 13, wherein:
the means for storing the location of the data processor includes means for determining the location of the data processor; and
the means for storing a set of radiation sources and intensities includes means for determining the set of radiation sources and intensities.
17. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for mitigating the impact of radiation induced soft errors in a data processor incorporating integrated circuits, said method steps comprising:
determining the location of said data processor;
determining a set of radiation sources and intensities at said location;
estimating the soft error rate of said data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value; and
modifying said data processor in response to said estimate value at times said estimate value exceeds a predetermined value.
18. A program storage device according to claim 17, wherein said step of determining a set of radiation sources and intensities includes the step of assessing radiation sources including background sources comprising neutrons, protons and pions.
19. A program storage device according to claim 17, wherein said step of estimating the soft error rate includes the step of estimating the soft error rate as a function of integrated circuit technology, dopant profiles and critical dimensions.
20. A method of mitigating the impact of radiation induced soft errors in a data processor incorporating integrated circuits, the method comprising the steps of:
providing the data processor with a defined procedure for obtaining a value representing an estimate of the soft error rate of the data processor as a function of the radiation intensity at the geographic location of the data processor and geometric characteristics of said integrated circuits;
inputting to the data processor a signal indicating the geographic location of the data processor;
the data processor using said procedure and said signal to provide an estimate value for the soft error rate of the data processor; and
modifying said data processor or data processing in response to said estimate value at times said estimate value exceeds a predetermined value.
21. A method according to claim 20, wherein the providing step includes the step of providing the data processor with a look-up table having a multitude of estimate values as a function of geographic location and time.
22. A method according to claim 21, wherein the step of providing the look-up table includes the step of determining the values of the look-up table by determining a set of radiation sources and intensities at a multitude of geographic locations.
23. A method according to claim 20, wherein the providing step includes the step of providing the data processor with an algorithm to calculate said estimate value as a function of geographic location and time.
24. A method according to claim 20, wherein the modifying step includes the step of modifying hardware configuration of the data processor.
25. A method according to claim 20, wherein the modifying step includes the step of modifying operation of software run on the data processor.
26. A method according to claim 20, wherein the data processor is part of a network of computers, and the modifying step includes the step of transferring operations of selected functions from the data processor to another computer of the network.
27. A method according to claim 20, wherein the data processor is mobile.